[Mlir-commits] [mlir] c28c8a0 - [MLIR][XeGPU] Add two 8bit float types F8E4M3FN and F8E5M2 to valid XeGPU float type. (#169420)

[llvmlistbot at llvm.org]

Author: Sang Ik Lee
Date: 2026-01-23T08:43:07-08:00
New Revision: c28c8a0056110dfd4689b7c0f0a2d034a6e5b2ab

URL: https://github.com/llvm/llvm-project/commit/c28c8a0056110dfd4689b7c0f0a2d034a6e5b2ab
DIFF: https://github.com/llvm/llvm-project/commit/c28c8a0056110dfd4689b7c0f0a2d034a6e5b2ab.diff

LOG: [MLIR][XeGPU] Add two 8bit float types F8E4M3FN and F8E5M2 to valid XeGPU float type. (#169420)

These float types are already part of MLIR built in types.
This PR just adds them as valid float types for XeGPU dialect.
For bit format of the two float types, see 
https://onnx.ai/onnx/technical/float8.html

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td

Removed: 
    


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diff  --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
index 91f362ce07f69..d9a785c869c3c 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
@@ -15,7 +15,7 @@ include "mlir/IR/BuiltinTypes.td"
 
 def XeGPU_IntType : AnyTypeOf<[I1, I<4>, I8, I16, I32, I64, SI1, SI8, SI16,
                                SI32, SI64, UI1, UI8, UI16, UI32, UI64]>;
-def XeGPU_FloatType : AnyTypeOf<[F16, F32, F64, BF16, TF32]>;
+def XeGPU_FloatType : AnyTypeOf<[F8E4M3FN, F8E5M2, F16, F32, F64, BF16, TF32]>;
 def XeGPU_ScalarType: AnyTypeOf<[XeGPU_IntType, XeGPU_FloatType]>;
 def XeGPU_PointerType : AnyTypeOf<[UI64, UI32, I64, I32]>;
 def XeGPU_BaseAddrType