[Mlir-commits] [mlir] [mlir][linalg] Update createWriteOrMaskedWrite (PR #174810)

[Andrzej Warzyński]

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@@ -26,13 +26,17 @@ func.func private @insert_slice_static_sizes(%source: tensor<?x3x?x1xi32>) -> te
 // CHECK-DAG:       %[[C_1:.*]] = arith.constant 1 : index
 // CHECK:           %[[MASK_READ:.*]] = vector.create_mask %[[C_5]], %[[C_1]] : vector<8x1xi1>
 // CHECK:           %[[READ:.*]] = vector.mask %[[MASK_READ]] { vector.transfer_read %[[SRC_SLICE]][%[[C_0]], %[[C_0]]], %[[PAD]] {{.*}} : tensor<5x1xi32>, vector<8x1xi32> } : vector<8x1xi1> -> vector<8x1xi32>
-// CHECK:           %[[C_0_1:.*]] = arith.constant 0 : index
+// CHECK:           %[[C_0_2:.*]] = arith.constant 0 : index
 // CHECK:           %[[C_5_1:.*]] = arith.constant 5 : index
+// CHECK:           %[[SUBI_0:.*]] = arith.subi %[[C_5_1]], %[[C_0_2]] : index
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banach-space wrote:

Done: https://github.com/llvm/llvm-project/pull/174810/commits/1d755462df0321e8af197f8fd71baba49a670144

https://github.com/llvm/llvm-project/pull/174810