[Mlir-commits] [mlir] [mlir][AMDGPU] Allow packing of exactly 4 elements. (PR #181843)

[llvmlistbot at llvm.org]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Muzammiluddin Syed (Muzammiluddin-Syed-ECE)

<details>
<summary>Changes</summary>

Fixes incorrect forgoing of packing.

---
Full diff: https://github.com/llvm/llvm-project/pull/181843.diff


1 Files Affected:

- (modified) mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp (+2-2) 


``````````diff
diff --git a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
index f9f11c1f9e540..f452d2de15dc8 100644
--- a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
+++ b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
@@ -1145,9 +1145,9 @@ struct PackScales final : OpRewritePattern<ScaledMFMAOp> {
       }
 
       int64_t numElements = scaleSrcType.getNumElements();
-      if (numElements <= 4) {
+      if (numElements < 4) {
         return rewriter.notifyMatchFailure(
-            op, "no packing if # of scales less than four");
+            op, "do not pack if # of scales less than four");
       }
 
       // Find a linearized idx using the size and offsets of the extract op.

``````````

</details>


https://github.com/llvm/llvm-project/pull/181843