[Mlir-commits] [mlir] [mlir][AMDGPU] Allow packing of exactly 4 elements. (PR #181843)

[Muzammiluddin Syed]

https://github.com/Muzammiluddin-Syed-ECE created https://github.com/llvm/llvm-project/pull/181843

Fixes incorrect forgoing of packing.

>From e804d9cbc8e9fc1aededf9e399ef5d0077be6937 Mon Sep 17 00:00:00 2001
From: Muzammiluddin Syed <muzasyed at amd.com>
Date: Tue, 17 Feb 2026 09:46:37 -0600
Subject: [PATCH] [mlir][AMDGPU] Allow packing of exactly 4 elements.

Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
---
 mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
index f9f11c1f9e540..f452d2de15dc8 100644
--- a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
+++ b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
@@ -1145,9 +1145,9 @@ struct PackScales final : OpRewritePattern<ScaledMFMAOp> {
       }
 
       int64_t numElements = scaleSrcType.getNumElements();
-      if (numElements <= 4) {
+      if (numElements < 4) {
         return rewriter.notifyMatchFailure(
-            op, "no packing if # of scales less than four");
+            op, "do not pack if # of scales less than four");
       }
 
       // Find a linearized idx using the size and offsets of the extract op.