[Mlir-commits] [clang] [llvm] [mlir] [AMDGPU] Fix missing cache bypass scope on seq_cst buffer fat pointer atomics (PR #213585)

[Krzysztof Drewniak]

================
@@ -1556,6 +1556,9 @@ class SplitPtrStructs : public InstVisitor<SplitPtrStructs, PtrParts> {
   void setAlign(CallInst *Intr, Align A, unsigned RsrcArgIdx);
   void insertPreMemOpFence(AtomicOrdering Order, SyncScope::ID SSID);
   void insertPostMemOpFence(AtomicOrdering Order, SyncScope::ID SSID);
+  // Empty when the access is not atomic.
+  SmallVector<OperandBundleDef, 1> getAtomicityBundle(AtomicOrdering Order,
----------------
krzysz00 wrote:

Quick question now that I've read this file more thoroughly - do we actually *need* `instertPreMemOpFence` and `insertPostMemOpFence` now that we're represeting atomicity on the operation ... or would that require a wider LLVM change?

I'll argue that if we make a generic `atomicity` bundle, we can teach LLVM proper about it and therefore get the same sort of treatment a normal atomic would get.

https://github.com/llvm/llvm-project/pull/213585