[Mlir-commits] [clang] [llvm] [mlir] [clang][NVPTX][MLIR][NVVM] Add overloaded fadd intrinsics (PR #217336)

[Durgadoss R]

================
@@ -7017,22 +7018,44 @@ static SDValue sinkProxyReg(SDValue R, SDValue Chain,
   }
 }
 
-static unsigned getF16SubOpc(Intrinsic::ID AddIntrinsicID) {
-  switch (AddIntrinsicID) {
+static unsigned getFAddWithNegOpcode(EVT VT, Intrinsic::ID IID,
+                                     APFloat::roundingMode RoundingMode) {
+  const bool IsFTZ = nvvm::FAddShouldFTZ(IID);
+  switch (VT.getScalarType().getSimpleVT().SimpleTy) {
+  case MVT::f16:
+    if (nvvm::FAddShouldSaturate(IID))
+      return IsFTZ ? NVPTXISD::SUB_RN_FTZ_SAT : NVPTXISD::SUB_RN_SAT;
+    return IsFTZ ? NVPTXISD::SUB_RN_FTZ : NVPTXISD::SUB_RN;
----------------
durga4github wrote:

optional: can a 2d array simplify this?
```
// [IsSat][IsFTZ] -> NVPTXISD opcode for f16
static const unsigned SubOpcF16[2][2] = {
      {NVPTXISD::SUB_RN,     NVPTXISD::SUB_RN_FTZ},
      {NVPTXISD::SUB_RN_SAT, NVPTXISD::SUB_RN_FTZ_SAT},
};
```


https://github.com/llvm/llvm-project/pull/217336