[Mlir-commits] [clang] [llvm] [mlir] [clang][NVPTX][MLIR][NVVM] Add overloaded fadd intrinsics (PR #217336)

[Durgadoss R]

================
@@ -7017,22 +7018,44 @@ static SDValue sinkProxyReg(SDValue R, SDValue Chain,
   }
 }
 
-static unsigned getF16SubOpc(Intrinsic::ID AddIntrinsicID) {
-  switch (AddIntrinsicID) {
+static unsigned getFAddWithNegOpcode(EVT VT, Intrinsic::ID IID,
+                                     APFloat::roundingMode RoundingMode) {
+  const bool IsFTZ = nvvm::FAddShouldFTZ(IID);
+  switch (VT.getScalarType().getSimpleVT().SimpleTy) {
+  case MVT::f16:
+    if (nvvm::FAddShouldSaturate(IID))
+      return IsFTZ ? NVPTXISD::SUB_RN_FTZ_SAT : NVPTXISD::SUB_RN_SAT;
+    return IsFTZ ? NVPTXISD::SUB_RN_FTZ : NVPTXISD::SUB_RN;
+  case MVT::bf16:
+    return NVPTXISD::SUB_RN;
+  case MVT::f32:
+    if (!VT.isVector() || nvvm::FAddShouldSaturate(IID))
+      return 0;
+    switch (RoundingMode) {
+    case APFloat::rmNearestTiesToEven:
+      return IsFTZ ? NVPTXISD::SUB_RN_FTZ : NVPTXISD::SUB_RN;
+    case APFloat::rmTowardZero:
+      return IsFTZ ? NVPTXISD::SUB_RZ_FTZ : NVPTXISD::SUB_RZ;
+    case APFloat::rmTowardNegative:
+      return IsFTZ ? NVPTXISD::SUB_RM_FTZ : NVPTXISD::SUB_RM;
+    case APFloat::rmTowardPositive:
+      return IsFTZ ? NVPTXISD::SUB_RP_FTZ : NVPTXISD::SUB_RP;
----------------
durga4github wrote:

can a 2d array make it less verbose?
```
    static const unsigned SubOpc[4][2] = {
      {NVPTXISD::SUB_RN, NVPTXISD::SUB_RN_FTZ},
      {NVPTXISD::SUB_RZ, NVPTXISD::SUB_RZ_FTZ},
      {NVPTXISD::SUB_RM, NVPTXISD::SUB_RM_FTZ},
      {NVPTXISD::SUB_RP, NVPTXISD::SUB_RP_FTZ},
    };
```

https://github.com/llvm/llvm-project/pull/217336