[Mlir-commits] [clang] [llvm] [mlir] [AMDGPU] Fix missing cache bypass scope on seq_cst buffer fat pointer atomics (PR #213585)

[Krzysztof Drewniak]

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@@ -1872,6 +1875,17 @@ void SplitPtrStructs::setAlign(CallInst *Intr, Align A, unsigned RsrcArgIdx) {
   Intr->addParamAttr(RsrcArgIdx, Attribute::getWithAlignment(Ctx, A));
 }
 
+Value *SplitPtrStructs::getScopeMDArg(AtomicOrdering Order,
+                                      SyncScope::ID SSID) {
+  LLVMContext &Ctx = IRB.getContext();
+  // An empty MDNode means not atomic. The system scope also has an empty
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krzysz00 wrote:

I don't think it does - I think it means "default scope", so probably system-wide.

https://github.com/llvm/llvm-project/pull/213585