[Mlir-commits] [clang] [llvm] [mlir] [AMDGPU] Fix missing cache bypass scope on seq_cst buffer fat pointer atomics (PR #213585)

[Krzysztof Drewniak]

================
@@ -1872,6 +1875,17 @@ void SplitPtrStructs::setAlign(CallInst *Intr, Align A, unsigned RsrcArgIdx) {
   Intr->addParamAttr(RsrcArgIdx, Attribute::getWithAlignment(Ctx, A));
 }
 
+Value *SplitPtrStructs::getScopeMDArg(AtomicOrdering Order,
+                                      SyncScope::ID SSID) {
+  LLVMContext &Ctx = IRB.getContext();
+  // An empty MDNode means not atomic. The system scope also has an empty
+  // name, so scope presence cannot be encoded by string emptiness alone.
+  if (Order == AtomicOrdering::NotAtomic)
----------------
krzysz00 wrote:

Yeah, this feels dubious.

https://github.com/llvm/llvm-project/pull/213585