[Mlir-commits] [mlir] [MLIR][NVVM] Add support for Convert Ops with rs-rounding mode (PR #165736)

[Durgadoss R]

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@@ -1921,6 +1922,95 @@ def NVVM_ConvertF6x2ToF16x2Op :
 def NVVM_ConvertF4x2ToF16x2Op :
   NVVM_ConvertToFP16x2Op_Base<"F4", I8, "F16">;
 
+//===----------------------------------------------------------------------===//
+// NVVM Stochastic Rounding Conversion Ops
+//===----------------------------------------------------------------------===//
+
+// Base class for conversions from F32x2 to FPx2 formats
+// (F16x2, BF16x2)
+// TODO: In separate PR, add .rn and .rz rounding variants for this conversion
+// as currently only support .rs rounding mode
+class NVVM_ConvertF32x2ToFPx2OpBase<string dstFormat, string mnemonic, Type resultType> :
+  NVVM_Op<mnemonic, [Pure, NVVMRequiresSMa<[100, 103]>]>,
+  Results<(outs resultType:$dst)>,
+  Arguments<(ins F32:$src_hi, F32:$src_lo, I32:$rbits,
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durga4github wrote:

Thanks for the _hi/_lo naming!

We can even add a line in the description section stating _hi refers to the operand `a` in PTX ISA and _lo points to operand `b`.

https://github.com/llvm/llvm-project/pull/165736