[Mlir-commits] [mlir] [MLIR][NVVM] Add support for Convert Ops with rs-rounding mode (PR #165736)

[Durgadoss R]

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@@ -2412,6 +2465,84 @@ Tcgen05CommitOp::getIntrinsicIDAndArgs(Operation &op,
     return TCGEN05_CP_2CTA(shape_mc, , is_2cta);                               \
   }()
 
+// Helper macros for F32x2 to FPx2 stochastic rounding intrinsics
+#define GET_F32x2_TO_F16x2_RS_ID(has_relu, has_satf)                           \
+  (has_relu ? (has_satf ? llvm::Intrinsic::nvvm_ff2f16x2_rs_relu_satfinite     \
+                        : llvm::Intrinsic::nvvm_ff2f16x2_rs_relu)              \
+            : (has_satf ? llvm::Intrinsic::nvvm_ff2f16x2_rs_satfinite          \
+                        : llvm::Intrinsic::nvvm_ff2f16x2_rs))
+
+#define GET_F32x2_TO_BF16x2_RS_ID(has_relu, has_satf)                          \
+  (has_relu ? (has_satf ? llvm::Intrinsic::nvvm_ff2bf16x2_rs_relu_satfinite    \
+                        : llvm::Intrinsic::nvvm_ff2bf16x2_rs_relu)             \
+            : (has_satf ? llvm::Intrinsic::nvvm_ff2bf16x2_rs_satfinite         \
+                        : llvm::Intrinsic::nvvm_ff2bf16x2_rs))
+
+llvm::Intrinsic::ID ConvertF32x2ToF16x2Op::getIntrinsicID() {
+  bool hasRelu = getRelu();
+  bool hasSatFinite = (getSat() == NVVM::SaturationMode::SATFINITE);
+  return GET_F32x2_TO_F16x2_RS_ID(hasRelu, hasSatFinite);
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durga4github wrote:

We are moving away from using macros as much as possible.
Since these checks are quite simple, would it make sense to move their implementation here itself?

https://github.com/llvm/llvm-project/pull/165736