[Mlir-commits] [mlir] [mlir][AMDGPU] Add scaled floating point conversion ops fp8 (PR #141554)
Tim Gymnich
llvmlistbot at llvm.org
Thu Jun 5 12:59:26 PDT 2025
================
@@ -112,6 +112,38 @@ def AMDGPU_ExtPackedFp8Op :
}];
}
+def AMDGPU_ScaledExtPackedOp
+ : AMDGPU_Op<"scaled_ext_packed", [Pure]>,
+ Arguments<(
+ ins AnyTypeOf<[VectorOfLengthAndType<[2, 3, 4], [F8E5M2, F8E4M3FN]>,
----------------
tgymnich wrote:
> ... and can you point me at the bf16 asymmetry?
There is `cvt.scalef32.f16.fp8` but I could not find `cvt.scalef32.bf16.fp8`.
> (Also, if there are non-packing instructions, we may want to only take even-sized vectors and let -arith-to-amdgpu handle the splitting into packed + non-packed instructions)
According to the function signature `cvt.scalef32.f16.fp8` still seems to be a packing instruction even though its missing the pk in the name.
https://github.com/llvm/llvm-project/pull/141554
More information about the Mlir-commits
mailing list