[Mlir-commits] [mlir] [mlir][AMDGPU] Add scaled floating point conversion ops fp8 (PR #141554)

[Krzysztof Drewniak]

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@@ -112,6 +112,38 @@ def AMDGPU_ExtPackedFp8Op :
   }];
 }
 
+def AMDGPU_ScaledExtPackedOp
+    : AMDGPU_Op<"scaled_ext_packed", [Pure]>,
+      Arguments<(
+          ins AnyTypeOf<[VectorOfLengthAndType<[2, 3, 4], [F8E5M2, F8E4M3FN]>,
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krzysz00 wrote:

I'm more thinking that if there _isn't_ a scalar instruction, we'll want to pad with 0s, but if there is one then never mind.

... and can you point me at the bf16 asymmetry? I can't think of one off the top of my head

(Also, if there are non-packing instructions, we may want to only take even-sized vectors and let -arith-to-amdgpu handle the splitting into packed + non-packed instructions)

https://github.com/llvm/llvm-project/pull/141554