[Mlir-commits] [mlir] [MLIR] Implement emulation of static indexing subbyte type vector stores (PR #115922)

[Andrzej Warzyński]

banach-space wrote:

> That is definitely handled in the code. :-)

OK, got it, thanks! This wasn't that obvious to me when reading the code, so I needed a bit of help (to be fair, you did document that). 

IMO, some extra comments would be helpful. In particular, I would appreciate an ASCII diagram. Something like this in `ConvertVectorStore`:
```cpp
Vector to store: vector<7xi2>
Value to store: 11 11 11 11 11 11 11 (all ones)

Destination: memref<12xi2>
Store offset: 2 (i.e. 4 bits into the 1st emulated byte).

MLIR: vector.store %val, %dest[%c2] : memref<12xi2>, vector<7xi2>

Destination memref before:

   Byte 0     Byte 1     Byte 2
+----------+----------+----------+
| 00000000 | 00000000 | 00000000 |
+----------+----------+----------+

Destination memref after:

   Byte 0     Byte 1     Byte 2
+----------+----------+----------+
| 00001111 | 11111111 | 11000000 |
+----------+----------+----------+

Note, stores to Byte 1 are "full-width" and hence don't require RMW (no need for atomicity). Stores
to Bytes 0 and Byte 2 are "partial", hence requiring RMW access (atomicity is required).
```

Feel free to re-use, modify.

https://github.com/llvm/llvm-project/pull/115922