[Mlir-commits] [mlir] [MLIR] Support non-atomic RMW option for emulated vector stores (PR #124887)

[Andrzej Warzyński]

================
@@ -0,0 +1,123 @@
+// RUN: mlir-opt --test-emulate-narrow-int="arith-compute-bitwidth=1 memref-load-bitwidth=8 atomic-store=false" --cse --split-input-file %s | FileCheck %s
+
+// TODO: remove memref.alloc() in the tests to eliminate noises.
+// memref.alloc exists here because sub-byte vector data types such as i2
+// are currently not supported as input arguments.
+
+func.func @vector_store_i2_const_index_two_partial_stores(%arg0: vector<3xi2>) {
+    %0 = memref.alloc() : memref<3x3xi2>
+    %c0 = arith.constant 0 : index
+    %c2 = arith.constant 2 : index
+    vector.store %arg0, %0[%c2, %c0] :memref<3x3xi2>, vector<3xi2>
+    return
+}
+// In this example, emit two RMW stores without full-width store.
+// Store bit [12:18), byte [1:2] to a 3-byte vector, both bytes are
+// accessed partially.
----------------
banach-space wrote:

Super helpful, but could it be unified with https://github.com/llvm/llvm-project/blob/main/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir#L374?

Suggestion for both files.
```suggestion
// Emit two RMW partial stores. Store 6 bits from the input vector (bits [12:18)), into bytes [1:2] from a 3-byte output memref. Due to partial storing, both bytes are accessed partially through masking.
```

https://github.com/llvm/llvm-project/pull/124887