[Mlir-commits] [mlir] 4149ec9 - [MLIR] Remove redundant verifier code in arith::ConstantOp

[Mehdi Amini]

Author: Mehdi Amini
Date: 2025-04-27T06:56:14-07:00
New Revision: 4149ec9970f10dc5f4bdc92563cad6229c8fa3ea

URL: https://github.com/llvm/llvm-project/commit/4149ec9970f10dc5f4bdc92563cad6229c8fa3ea
DIFF: https://github.com/llvm/llvm-project/commit/4149ec9970f10dc5f4bdc92563cad6229c8fa3ea.diff

LOG: [MLIR] Remove redundant verifier code in arith::ConstantOp

This is already checked by the `AllTypesMatch` traits defined in ODS.

Added: 
    

Modified: 
    mlir/lib/Dialect/Arith/IR/ArithOps.cpp

Removed: 
    


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diff  --git a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp
index e9545c3146b2f..3b308716c84dc 100644
--- a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp
+++ b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp
@@ -207,11 +207,6 @@ void arith::ConstantOp::getAsmResultNames(
 /// or float like.
 LogicalResult arith::ConstantOp::verify() {
   auto type = getType();
-  // The value's type must match the return type.
-  if (getValue().getType() != type) {
-    return emitOpError() << "value type " << getValue().getType()
-                         << " must match return type: " << type;
-  }
   // Integer values must be signless.
   if (llvm::isa<IntegerType>(type) &&
       !llvm::cast<IntegerType>(type).isSignless())