[Mlir-commits] [mlir] [mlir][nvvm] Expand sitofp/uitofp to faster ops (PR #107001)

[Mehdi Amini]

joker-eph wrote:

> Doing this optimization in LLVM would only work for i16->fp32 because the NVPTX backend has no i8 registers and promotes them to i16.

I didn't follow this explanation: can you elaborate a bit more which one of the cases in the tests couldn't be done in LLVM IR?

https://github.com/llvm/llvm-project/pull/107001