[Mlir-commits] [mlir] Allow 16 bit floating point operand for LLVM_AtomicRMWOp (PR #110553)

[Giuseppe Rossini]

================
@@ -139,6 +139,16 @@ class LLVM_VectorOf<Type element> : Type<
 class LLVM_ScalarOrVectorOf<Type element> :
     AnyTypeOf<[element, LLVM_VectorOf<element>]>;
 
+// Type constraint accepting an LLVM fixed vector type with an additional constraint
+// on the vector element type.
+class LLVM_FixedVectorOf<Type element> : Type<
+  And<[LLVM_AnyFixedVector.predicate,
----------------
giuseros wrote:

What I was pointing to was that you can use:
```
def LLVM_AtomicRMWType
    : AnyTypeOf<[LLVM_AnyFloat, LLVM_AnyPointer, AnySignlessInteger, LLVM_AnyFixedVector]>;
```
And then check for fp16 in the verifier. In this way you don't have to add `LLVM_FixedVectorOf`.

https://github.com/llvm/llvm-project/pull/110553