[Mlir-commits] [mlir] [mlir][ArmSME] Support widening outer products (PR #78975)

[Cullen Rhodes]

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@@ -410,4 +410,8 @@ def ConvertToSvboolIntrOp :
     /*overloadedResults=*/[]>,
     Arguments<(ins SVEPredicate:$mask)>;
 
+def Zip1IntrOp :
+  ArmSVE_IntrBinaryOverloadedOp<"zip1">,
+  Arguments<(ins AnyScalableVector, AnyScalableVector)>;
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c-rhodes wrote:

You're right Ben these constraints don't match the ISA, although I should point out the intrinsic definitions in the backend are typically very relaxed as well, for zip1 see:

https://github.com/llvm/llvm-project/blob/b0763a1ae940d60d8f558f85216382bc6695a1e3/llvm/include/llvm/IR/IntrinsicsAArch64.td#L130-L132

https://github.com/llvm/llvm-project/blob/b0763a1ae940d60d8f558f85216382bc6695a1e3/llvm/include/llvm/IR/IntrinsicsAArch64.td#L1927

I suspect the intrinsic definitions in the SVE dialect have followed suit, that's not to say we can't do better in MLIR however, and for SME that's been the case, the MLIR constraints are tighter than the LLVM ones.

> Also, @c-rhodes , thinking how to split this massive patch - would you mind moving zip1 to a dedicated PR?

sure 👍 

https://github.com/llvm/llvm-project/pull/78975