[Mlir-commits] [mlir] [mlir][ArmSME] Support widening outer products (PR #78975)

[Benjamin Maxwell]

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@@ -410,4 +410,8 @@ def ConvertToSvboolIntrOp :
     /*overloadedResults=*/[]>,
     Arguments<(ins SVEPredicate:$mask)>;
 
+def Zip1IntrOp :
+  ArmSVE_IntrBinaryOverloadedOp<"zip1">,
+  Arguments<(ins AnyScalableVector, AnyScalableVector)>;
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MacDue wrote:

> Why? As in, what's the difference between this and other intrinsics? Is it something from the ISA that I am missing?

There's no difference, I think they all should be using SVEVector as their types. I think these intrinsics (that very closely map to hardware instructions), have to have types that match actual hardware sizes, or they'll fail to lower: https://godbolt.org/z/o5c941Gb3 (as a random example). 

https://github.com/llvm/llvm-project/pull/78975