[Mlir-commits] [mlir] [mlir][NFC] Fix comment explaining ConverVectorLoad (PR #67864)

[llvmlistbot at llvm.org]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

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<details>
<summary>Changes</summary>

The new number of elements should be the original one divided by a scale factor computed from old and new bit width.

---
Full diff: https://github.com/llvm/llvm-project/pull/67864.diff


1 Files Affected:

- (modified) mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp (+1-1) 


``````````diff
diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
index 6a186ae67eaa676..94300291dcd7d23 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
@@ -67,7 +67,7 @@ struct ConvertVectorLoad final : OpConversionPattern<vector::LoadOp> {
     //
     // can be replaced with
     //
-    // %1 = vector.load %0[%linear_index] : memref<12xi8>, vector<2xi8>
+    // %1 = vector.load %0[%linear_index] : memref<6xi8>, vector<2xi8>
     // %2 = vector.bitcast %1 : vector<2xi8> to vector<4xi4>
     //
     // TODO: Currently, only the even number of elements loading is supported.

``````````

</details>


https://github.com/llvm/llvm-project/pull/67864