[Mlir-commits] [mlir] [mlir][NFC] Fix comment explaining ConverVectorLoad (PR #67864)

[llvmlistbot at llvm.org]

https://github.com/tyb0807 created https://github.com/llvm/llvm-project/pull/67864

The new number of elements should be the original one divided by a scale factor computed from old and new bit width.

>From e822ce16ce86e804b63edcacfccc5f2c01918656 Mon Sep 17 00:00:00 2001
From: tyb0807 <vuson at google.com>
Date: Fri, 29 Sep 2023 22:33:27 +0000
Subject: [PATCH] [mlir][NFC] Fix comment explaining ConverVectorLoad

The new number of elements should be the original one divided by a scale factor computed from old and new bit width.
---
 mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
index 6a186ae67eaa676..94300291dcd7d23 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
@@ -67,7 +67,7 @@ struct ConvertVectorLoad final : OpConversionPattern<vector::LoadOp> {
     //
     // can be replaced with
     //
-    // %1 = vector.load %0[%linear_index] : memref<12xi8>, vector<2xi8>
+    // %1 = vector.load %0[%linear_index] : memref<6xi8>, vector<2xi8>
     // %2 = vector.bitcast %1 : vector<2xi8> to vector<4xi4>
     //
     // TODO: Currently, only the even number of elements loading is supported.