[Mlir-commits] [mlir] [mlir][spirv][webgpu] Add lowering of IAddCarry to IAdd (PR #68495)

[Finn Plummer]

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@@ -133,6 +133,48 @@ Value lowerExtendedMultiplication(Operation *mulOp, PatternRewriter &rewriter,
       loc, mulOp->getResultTypes().front(), llvm::ArrayRef({low, high}));
 }
 
+Value lowerCarryAddition(Operation *addOp, PatternRewriter &rewriter, Value lhs,
+                         Value rhs) {
+  Location loc = addOp->getLoc();
+  Type argTy = lhs.getType();
+  // Emulate 64-bit addition by splitting each input element of type i32 to
+  // i16 similar to above in lowerExtendedMultiplication. We then expand
+  // to 3 additions:
+  //    - Add two low digits into low resut
+  //    - Add two high digits into high result
+  //    - Add the carry from low result to high result
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inbelic wrote:

Nice, that feels much better. From now reading the linked spec a second time, it is clear to me that we can expect the overflow behaviour to be how we would want. I was not diligent enough when reading the "avoid overflow and underflow" statement the first time, whoops.

https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#_arithmetic_instructions

https://github.com/llvm/llvm-project/pull/68495