[Mlir-commits] [mlir] [MLIR][Transforms] Fix Mem2Reg removal order to respect dominance (PR #68687)

[Tobias Gysi]

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@@ -683,3 +683,16 @@ llvm.func @no_inner_alloca_promotion(%arg: i64) -> i64 {
   // CHECK: llvm.return %[[RES]] : i64
   llvm.return %2 : i64
 }
+
+// -----
+
+// CHECK-LABEL: @transitive_reaching_def
+llvm.func @transitive_reaching_def() -> !llvm.ptr {
+  %0 = llvm.mlir.constant(1 : i32) : i32
+  // CHECK-NOT: alloca
+  %3 = llvm.alloca %0 x !llvm.ptr {alignment = 8 : i64} : (i32) -> !llvm.ptr
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gysit wrote:

ultra nit: can you maybe number %0, %1, %2, %3

https://github.com/llvm/llvm-project/pull/68687