[Mlir-commits] [mlir] a7baaab - Use APInt::isZero instead of APInt::isNulLValue (NFC)
Kazu Hirata
llvmlistbot at llvm.org
Sun Feb 19 22:24:05 PST 2023
Author: Kazu Hirata
Date: 2023-02-19T22:23:58-08:00
New Revision: a7baaab9526bd928aff37455b7b65ed523ea36e1
URL: https://github.com/llvm/llvm-project/commit/a7baaab9526bd928aff37455b7b65ed523ea36e1
DIFF: https://github.com/llvm/llvm-project/commit/a7baaab9526bd928aff37455b7b65ed523ea36e1.diff
LOG: Use APInt::isZero instead of APInt::isNulLValue (NFC)
Note that APInt::isNullValue has been soft-deprecated in favor of
APInt::isZero.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
mlir/lib/Dialect/Arith/IR/ArithOps.cpp
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
mlir/lib/Dialect/Shape/IR/Shape.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f8fd1cefb9b98..e5dba3e757f7b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -24602,12 +24602,9 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
}
}
// TODO: Should we try to mask with N1 as well?
- if (!IsInLaneMask &&
- (!DemandedLHS.isNullValue() || !DemandedRHS.isNullValue()) &&
- (DemandedLHS.isNullValue() ||
- DAG.MaskedVectorIsZero(N0, DemandedLHS)) &&
- (DemandedRHS.isNullValue() ||
- DAG.MaskedVectorIsZero(N1, DemandedRHS))) {
+ if (!IsInLaneMask && (!DemandedLHS.isZero() || !DemandedRHS.isZero()) &&
+ (DemandedLHS.isZero() || DAG.MaskedVectorIsZero(N0, DemandedLHS)) &&
+ (DemandedRHS.isZero() || DAG.MaskedVectorIsZero(N1, DemandedRHS))) {
SDLoc DL(N);
EVT IntVT = VT.changeVectorElementTypeToInteger();
EVT IntSVT = VT.getVectorElementType().changeTypeToInteger();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index b1b22d883dc49..ce12b59aa4ed2 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5851,7 +5851,7 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
uint64_t Key = I.getOperand(3).getImm();
Register DiscReg = I.getOperand(4).getReg();
auto DiscVal = getIConstantVRegVal(DiscReg, MRI);
- bool IsDiscZero = DiscVal && DiscVal->isNullValue();
+ bool IsDiscZero = DiscVal && DiscVal->isZero();
if (Key > AArch64PACKey::LAST)
return false;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 377cba8eb9493..92481ba6c7a7d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -12131,8 +12131,8 @@ static bool isTargetShuffleEquivalent(MVT VT, ArrayRef<int> Mask,
}
return false;
}
- return (ZeroV1.isNullValue() || DAG.MaskedVectorIsZero(V1, ZeroV1)) &&
- (ZeroV2.isNullValue() || DAG.MaskedVectorIsZero(V2, ZeroV2));
+ return (ZeroV1.isZero() || DAG.MaskedVectorIsZero(V1, ZeroV1)) &&
+ (ZeroV2.isZero() || DAG.MaskedVectorIsZero(V2, ZeroV2));
}
// Check if the shuffle mask is suitable for the AVX vpunpcklwd or vpunpckhwd
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index f381649a5e7d5..c49b4a8df55fb 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -4468,7 +4468,7 @@ X86TTIImpl::getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
for (unsigned I = 0; I != NumLanesTotal; ++I) {
APInt LaneEltMask = WidenedDemandedElts.extractBits(
NumEltsPerLane, NumEltsPerLane * I);
- if (LaneEltMask.isNullValue())
+ if (LaneEltMask.isZero())
continue;
// FIXME: we don't need to extract if all non-demanded elements
// are legalization-inserted padding.
@@ -4549,7 +4549,7 @@ X86TTIImpl::getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
for (unsigned I = 0; I != NumLanesTotal; ++I) {
APInt LaneEltMask = WidenedDemandedElts.extractBits(
NumEltsPerLane, I * NumEltsPerLane);
- if (LaneEltMask.isNullValue())
+ if (LaneEltMask.isZero())
continue;
Cost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt,
CostKind, I * NumEltsPerLane, LaneTy);
diff --git a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp
index 775ee8466beef..d5fb08fd8b40d 100644
--- a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp
+++ b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp
@@ -708,7 +708,7 @@ OpFoldResult arith::RemUIOp::fold(FoldAdaptor adaptor) {
bool div0 = false;
auto result = constFoldBinaryOp<IntegerAttr>(adaptor.getOperands(),
[&](APInt a, const APInt &b) {
- if (div0 || b.isNullValue()) {
+ if (div0 || b.isZero()) {
div0 = true;
return a;
}
@@ -731,7 +731,7 @@ OpFoldResult arith::RemSIOp::fold(FoldAdaptor adaptor) {
bool div0 = false;
auto result = constFoldBinaryOp<IntegerAttr>(adaptor.getOperands(),
[&](APInt a, const APInt &b) {
- if (div0 || b.isNullValue()) {
+ if (div0 || b.isZero()) {
div0 = true;
return a;
}
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index 5e37409a8e20c..66766aa0b6d10 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -214,7 +214,7 @@ ParseResult AllocaOp::parse(OpAsmParser &parser, OperationState &result) {
if (!alignmentInt)
return parser.emitError(parser.getNameLoc(),
"expected integer alignment");
- if (alignmentInt.getValue().isNullValue())
+ if (alignmentInt.getValue().isZero())
result.attributes.erase("alignment");
}
@@ -1842,7 +1842,7 @@ ParseResult GlobalOp::parse(OpAsmParser &parser, OperationState &result) {
static bool isZeroAttribute(Attribute value) {
if (auto intValue = value.dyn_cast<IntegerAttr>())
- return intValue.getValue().isNullValue();
+ return intValue.getValue().isZero();
if (auto fpValue = value.dyn_cast<FloatAttr>())
return fpValue.getValue().isZero();
if (auto splatValue = value.dyn_cast<SplatElementsAttr>())
diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
index 92ab0cbbb5870..f6865b4107098 100644
--- a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
+++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
@@ -1736,7 +1736,7 @@ LogicalResult spirv::BranchConditionalOp::verify() {
return emitOpError("must have exactly two branch weights");
}
if (llvm::all_of(*weights, [](Attribute attr) {
- return attr.cast<IntegerAttr>().getValue().isNullValue();
+ return attr.cast<IntegerAttr>().getValue().isZero();
}))
return emitOpError("branch weights cannot both be zero");
}
diff --git a/mlir/lib/Dialect/Shape/IR/Shape.cpp b/mlir/lib/Dialect/Shape/IR/Shape.cpp
index 7e4d1250ba2e1..9af32fb5afe74 100644
--- a/mlir/lib/Dialect/Shape/IR/Shape.cpp
+++ b/mlir/lib/Dialect/Shape/IR/Shape.cpp
@@ -1132,7 +1132,7 @@ OpFoldResult DivOp::fold(FoldAdaptor adaptor) {
// negative. Rather, APInt rounds toward zero.
APInt quotient, remainder;
APInt::sdivrem(lhs.getValue(), rhs.getValue(), quotient, remainder);
- if (quotient.isNegative() && !remainder.isNullValue()) {
+ if (quotient.isNegative() && !remainder.isZero()) {
quotient -= 1;
}
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