[Mlir-commits] [mlir] f8f3db2 - Use APInt::count{l, r}_{zero, one} (NFC)
Kazu Hirata
llvmlistbot at llvm.org
Sun Feb 19 22:04:55 PST 2023
Author: Kazu Hirata
Date: 2023-02-19T22:04:47-08:00
New Revision: f8f3db27565cae8e07c2487f9714a32840c6d548
URL: https://github.com/llvm/llvm-project/commit/f8f3db27565cae8e07c2487f9714a32840c6d548
DIFF: https://github.com/llvm/llvm-project/commit/f8f3db27565cae8e07c2487f9714a32840c6d548.diff
LOG: Use APInt::count{l,r}_{zero,one} (NFC)
Added:
Modified:
clang-tools-extra/clang-tidy/bugprone/SuspiciousEnumUsageCheck.cpp
clang/lib/AST/ExprConstant.cpp
clang/lib/CodeGen/CGExprCXX.cpp
clang/lib/Lex/LiteralSupport.cpp
clang/lib/StaticAnalyzer/Checkers/UndefResultChecker.cpp
clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp
llvm/include/llvm/ADT/APInt.h
llvm/include/llvm/Support/KnownBits.h
llvm/lib/Analysis/BasicAliasAnalysis.cpp
llvm/lib/Analysis/ConstantFolding.cpp
llvm/lib/Analysis/DemandedBits.cpp
llvm/lib/Analysis/IVDescriptors.cpp
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/lib/Analysis/LazyValueInfo.cpp
llvm/lib/Analysis/ScalarEvolution.cpp
llvm/lib/Analysis/ValueTracking.cpp
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
llvm/lib/CodeGen/GlobalISel/Utils.cpp
llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/IR/ConstantRange.cpp
llvm/lib/IR/Instructions.cpp
llvm/lib/IR/Value.cpp
llvm/lib/Support/APFloat.cpp
llvm/lib/Support/APInt.cpp
llvm/lib/Support/DivisionByConstantInfo.cpp
llvm/lib/Support/KnownBits.cpp
llvm/lib/Target/AArch64/AArch64FastISel.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/lib/Target/Hexagon/HexagonGenExtract.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
llvm/lib/Transforms/Scalar/BDCE.cpp
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
llvm/unittests/IR/ConstantRangeTest.cpp
llvm/unittests/IR/MetadataTest.cpp
llvm/unittests/Support/DivisionByConstantTest.cpp
llvm/utils/TableGen/CodeGenSchedule.cpp
mlir/lib/AsmParser/AttributeParser.cpp
mlir/lib/Dialect/Math/IR/MathOps.cpp
mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
Removed:
################################################################################
diff --git a/clang-tools-extra/clang-tidy/bugprone/SuspiciousEnumUsageCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/SuspiciousEnumUsageCheck.cpp
index 3bd8350c83ddf..90e68d15e4c00 100644
--- a/clang-tools-extra/clang-tidy/bugprone/SuspiciousEnumUsageCheck.cpp
+++ b/clang-tools-extra/clang-tidy/bugprone/SuspiciousEnumUsageCheck.cpp
@@ -77,7 +77,7 @@ static bool isMaxValAllBitSetLiteral(const EnumDecl *EnumDec) {
});
if (const Expr *InitExpr = EnumConst->getInitExpr()) {
- return EnumConst->getInitVal().countTrailingOnes() ==
+ return EnumConst->getInitVal().countr_one() ==
EnumConst->getInitVal().getActiveBits() &&
isa<IntegerLiteral>(InitExpr->IgnoreImpCasts());
}
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index e44aa546aae6c..9d43ad1cfc528 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -2802,7 +2802,7 @@ static bool handleIntIntBinOp(EvalInfo &Info, const Expr *E, const APSInt &LHS,
// E1 x 2^E2 module 2^N.
if (LHS.isNegative())
Info.CCEDiag(E, diag::note_constexpr_lshift_of_negative) << LHS;
- else if (LHS.countLeadingZeros() < SA)
+ else if (LHS.countl_zero() < SA)
Info.CCEDiag(E, diag::note_constexpr_lshift_discards);
}
Result = LHS << SA;
@@ -12021,7 +12021,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
if (!Val)
return Error(E);
- return Success(Val.countLeadingZeros(), E);
+ return Success(Val.countl_zero(), E);
}
case Builtin::BI__builtin_constant_p: {
@@ -12067,7 +12067,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
if (!Val)
return Error(E);
- return Success(Val.countTrailingZeros(), E);
+ return Success(Val.countr_zero(), E);
}
case Builtin::BI__builtin_eh_return_data_regno: {
@@ -12087,7 +12087,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
if (!EvaluateInteger(E->getArg(0), Val, Info))
return false;
- unsigned N = Val.countTrailingZeros();
+ unsigned N = Val.countr_zero();
return Success(N == Val.getBitWidth() ? 0 : N + 1, E);
}
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index 40559b640dea9..68a7f831414a6 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -765,7 +765,7 @@ static llvm::Value *EmitCXXNewAllocSize(CodeGenFunction &CGF,
// wider than that, check whether it's already too big, and if so,
// overflow.
else if (numElementsWidth > sizeWidth &&
- numElementsWidth - sizeWidth > count.countLeadingZeros())
+ numElementsWidth - sizeWidth > count.countl_zero())
hasAnyOverflow = true;
// Okay, compute a count at the right width.
diff --git a/clang/lib/Lex/LiteralSupport.cpp b/clang/lib/Lex/LiteralSupport.cpp
index 38b68bde4b516..3efecc709334c 100644
--- a/clang/lib/Lex/LiteralSupport.cpp
+++ b/clang/lib/Lex/LiteralSupport.cpp
@@ -1758,7 +1758,7 @@ CharLiteralParser::CharLiteralParser(const char *begin, const char *end,
LitVal = 0;
for (size_t i = 0; i < NumCharsSoFar; ++i) {
// check for enough leading zeros to shift into
- multi_char_too_long |= (LitVal.countLeadingZeros() < 8);
+ multi_char_too_long |= (LitVal.countl_zero() < 8);
LitVal <<= 8;
LitVal = LitVal + (codepoint_buffer[i] & 0xFF);
}
diff --git a/clang/lib/StaticAnalyzer/Checkers/UndefResultChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/UndefResultChecker.cpp
index 2658b473a4775..f20b38a53151c 100644
--- a/clang/lib/StaticAnalyzer/Checkers/UndefResultChecker.cpp
+++ b/clang/lib/StaticAnalyzer/Checkers/UndefResultChecker.cpp
@@ -70,7 +70,7 @@ static bool isLeftShiftResultUnrepresentable(const BinaryOperator *B,
const llvm::APSInt *LHS = SB.getKnownValue(State, C.getSVal(B->getLHS()));
const llvm::APSInt *RHS = SB.getKnownValue(State, C.getSVal(B->getRHS()));
assert(LHS && RHS && "Values unknown, inconsistent state");
- return (unsigned)RHS->getZExtValue() > LHS->countLeadingZeros();
+ return (unsigned)RHS->getZExtValue() > LHS->countl_zero();
}
void UndefResultChecker::checkPostStmt(const BinaryOperator *B,
diff --git a/clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp b/clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp
index 40cdaef1bfa74..fc736dd452aab 100644
--- a/clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp
+++ b/clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp
@@ -288,7 +288,7 @@ BasicValueFactory::evalAPSInt(BinaryOperator::Opcode Op,
if (V1.isSigned() && V1.isNegative())
return nullptr;
- if (V1.isSigned() && Amt > V1.countLeadingZeros())
+ if (V1.isSigned() && Amt > V1.countl_zero())
return nullptr;
}
diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h
index aa78d648c46a7..61c878608b5b9 100644
--- a/llvm/include/llvm/ADT/APInt.h
+++ b/llvm/include/llvm/ADT/APInt.h
@@ -443,8 +443,8 @@ class [[nodiscard]] APInt {
if (isNonNegative())
return false;
// NegatedPowerOf2 - shifted mask in the top bits.
- unsigned LO = countLeadingOnes();
- unsigned TZ = countTrailingZeros();
+ unsigned LO = countl_one();
+ unsigned TZ = countr_zero();
return (LO + TZ) == BitWidth;
}
@@ -500,7 +500,7 @@ class [[nodiscard]] APInt {
return isShiftedMask_64(U.VAL);
unsigned Ones = countPopulationSlowCase();
unsigned LeadZ = countLeadingZerosSlowCase();
- return (Ones + LeadZ + countTrailingZeros()) == BitWidth;
+ return (Ones + LeadZ + countr_zero()) == BitWidth;
}
/// Return true if this APInt value contains a non-empty sequence of ones with
@@ -1460,7 +1460,7 @@ class [[nodiscard]] APInt {
/// This function returns the number of active bits which is defined as the
/// bit width minus the number of leading zeros. This is used in several
/// computations to see how "wide" the value is.
- unsigned getActiveBits() const { return BitWidth - countLeadingZeros(); }
+ unsigned getActiveBits() const { return BitWidth - countl_zero(); }
/// Compute the number of active words in the value of this APInt.
///
@@ -1579,7 +1579,7 @@ class [[nodiscard]] APInt {
/// Computes the number of leading bits of this APInt that are equal to its
/// sign bit.
unsigned getNumSignBits() const {
- return isNegative() ? countLeadingOnes() : countLeadingZeros();
+ return isNegative() ? countl_one() : countl_zero();
}
/// Count the number of trailing zero bits.
diff --git a/llvm/include/llvm/Support/KnownBits.h b/llvm/include/llvm/Support/KnownBits.h
index caa0aef93e028..26b62fb4e3828 100644
--- a/llvm/include/llvm/Support/KnownBits.h
+++ b/llvm/include/llvm/Support/KnownBits.h
@@ -230,24 +230,16 @@ struct KnownBits {
KnownBits makeGE(const APInt &Val) const;
/// Returns the minimum number of trailing zero bits.
- unsigned countMinTrailingZeros() const {
- return Zero.countTrailingOnes();
- }
+ unsigned countMinTrailingZeros() const { return Zero.countr_one(); }
/// Returns the minimum number of trailing one bits.
- unsigned countMinTrailingOnes() const {
- return One.countTrailingOnes();
- }
+ unsigned countMinTrailingOnes() const { return One.countr_one(); }
/// Returns the minimum number of leading zero bits.
- unsigned countMinLeadingZeros() const {
- return Zero.countLeadingOnes();
- }
+ unsigned countMinLeadingZeros() const { return Zero.countl_one(); }
/// Returns the minimum number of leading one bits.
- unsigned countMinLeadingOnes() const {
- return One.countLeadingOnes();
- }
+ unsigned countMinLeadingOnes() const { return One.countl_one(); }
/// Returns the number of times the sign bit is replicated into the other
/// bits.
@@ -270,24 +262,16 @@ struct KnownBits {
}
/// Returns the maximum number of trailing zero bits possible.
- unsigned countMaxTrailingZeros() const {
- return One.countTrailingZeros();
- }
+ unsigned countMaxTrailingZeros() const { return One.countr_zero(); }
/// Returns the maximum number of trailing one bits possible.
- unsigned countMaxTrailingOnes() const {
- return Zero.countTrailingZeros();
- }
+ unsigned countMaxTrailingOnes() const { return Zero.countr_zero(); }
/// Returns the maximum number of leading zero bits possible.
- unsigned countMaxLeadingZeros() const {
- return One.countLeadingZeros();
- }
+ unsigned countMaxLeadingZeros() const { return One.countl_zero(); }
/// Returns the maximum number of leading one bits possible.
- unsigned countMaxLeadingOnes() const {
- return Zero.countLeadingZeros();
- }
+ unsigned countMaxLeadingOnes() const { return Zero.countl_zero(); }
/// Returns the number of bits known to be one.
unsigned countMinPopulation() const { return One.popcount(); }
diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index dc728c1cbfebc..b677eae2c76c6 100644
--- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -1134,8 +1134,8 @@ AliasResult BasicAAResult::aliasGEP(
const APInt &Scale = Index.Scale;
APInt ScaleForGCD = Scale;
if (!Index.IsNSW)
- ScaleForGCD = APInt::getOneBitSet(Scale.getBitWidth(),
- Scale.countTrailingZeros());
+ ScaleForGCD =
+ APInt::getOneBitSet(Scale.getBitWidth(), Scale.countr_zero());
if (i == 0)
GCD = ScaleForGCD.abs();
diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp
index 5a6490a4ca13c..8fe0799128c2e 100644
--- a/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/llvm/lib/Analysis/ConstantFolding.cpp
@@ -2801,9 +2801,9 @@ static Constant *ConstantFoldScalarCall2(StringRef Name,
if (!C0)
return Constant::getNullValue(Ty);
if (IntrinsicID == Intrinsic::cttz)
- return ConstantInt::get(Ty, C0->countTrailingZeros());
+ return ConstantInt::get(Ty, C0->countr_zero());
else
- return ConstantInt::get(Ty, C0->countLeadingZeros());
+ return ConstantInt::get(Ty, C0->countl_zero());
case Intrinsic::abs:
assert(C1 && "Must be constant int");
diff --git a/llvm/lib/Analysis/DemandedBits.cpp b/llvm/lib/Analysis/DemandedBits.cpp
index 101d0ab76722b..e5d693a220d1e 100644
--- a/llvm/lib/Analysis/DemandedBits.cpp
+++ b/llvm/lib/Analysis/DemandedBits.cpp
@@ -170,7 +170,7 @@ void DemandedBits::determineLiveOperandBits(
case Intrinsic::smin:
// If low bits of result are not demanded, they are also not demanded
// for the min/max operands.
- AB = APInt::getBitsSetFrom(BitWidth, AOut.countTrailingZeros());
+ AB = APInt::getBitsSetFrom(BitWidth, AOut.countr_zero());
break;
}
}
diff --git a/llvm/lib/Analysis/IVDescriptors.cpp b/llvm/lib/Analysis/IVDescriptors.cpp
index ead48e4028152..38b1a1d0b0bbd 100644
--- a/llvm/lib/Analysis/IVDescriptors.cpp
+++ b/llvm/lib/Analysis/IVDescriptors.cpp
@@ -107,7 +107,7 @@ static std::pair<Type *, bool> computeRecurrenceType(Instruction *Exit,
// must be positive (i.e., IsSigned = false), because if this were not the
// case, the sign bit would have been demanded.
auto Mask = DB->getDemandedBits(Exit);
- MaxBitWidth = Mask.getBitWidth() - Mask.countLeadingZeros();
+ MaxBitWidth = Mask.getBitWidth() - Mask.countl_zero();
}
if (MaxBitWidth == DL.getTypeSizeInBits(Exit->getType()) && AC && DT) {
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp
index 372448b064729..38dc5fb3ee0e6 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -1163,9 +1163,9 @@ static Value *simplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1,
// at least as many trailing zeros as the divisor to divide evenly. If it has
// less trailing zeros, then the result must be poison.
const APInt *DivC;
- if (IsExact && match(Op1, m_APInt(DivC)) && DivC->countTrailingZeros()) {
+ if (IsExact && match(Op1, m_APInt(DivC)) && DivC->countr_zero()) {
KnownBits KnownOp0 = computeKnownBits(Op0, Q.DL, 0, Q.AC, Q.CxtI, Q.DT);
- if (KnownOp0.countMaxTrailingZeros() < DivC->countTrailingZeros())
+ if (KnownOp0.countMaxTrailingZeros() < DivC->countr_zero())
return PoisonValue::get(Op0->getType());
}
diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp
index 944b4a2938daf..7bb66f2c96628 100644
--- a/llvm/lib/Analysis/LazyValueInfo.cpp
+++ b/llvm/lib/Analysis/LazyValueInfo.cpp
@@ -1125,7 +1125,7 @@ static ValueLatticeElement getValueFromICmpCondition(Value *Val, ICmpInst *ICI,
// bit of Mask.
if (EdgePred == ICmpInst::ICMP_NE && !Mask->isZero() && C->isZero()) {
return ValueLatticeElement::getRange(ConstantRange::getNonEmpty(
- APInt::getOneBitSet(BitWidth, Mask->countTrailingZeros()),
+ APInt::getOneBitSet(BitWidth, Mask->countr_zero()),
APInt::getZero(BitWidth)));
}
}
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 3bbb818654fd7..36cb779787066 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -984,7 +984,7 @@ static const SCEV *BinomialCoefficient(const SCEV *It, unsigned K,
unsigned T = 1;
for (unsigned i = 3; i <= K; ++i) {
APInt Mult(W, i);
- unsigned TwoFactors = Mult.countTrailingZeros();
+ unsigned TwoFactors = Mult.countr_zero();
T += TwoFactors;
Mult.lshrInPlace(TwoFactors);
OddFactorial *= Mult;
@@ -3455,7 +3455,7 @@ const SCEV *ScalarEvolution::getUDivExpr(const SCEV *LHS,
// its operands.
// TODO: Generalize this to non-constants by using known-bits information.
Type *Ty = LHS->getType();
- unsigned LZ = RHSC->getAPInt().countLeadingZeros();
+ unsigned LZ = RHSC->getAPInt().countl_zero();
unsigned MaxShiftAmt = getTypeSizeInBits(Ty) - LZ - 1;
// For non-power-of-two values, effectively round the value up to the
// nearest power of two.
@@ -6313,7 +6313,7 @@ const SCEV *ScalarEvolution::createNodeForGEP(GEPOperator *GEP) {
uint32_t ScalarEvolution::GetMinTrailingZerosImpl(const SCEV *S) {
switch (S->getSCEVType()) {
case scConstant:
- return cast<SCEVConstant>(S)->getAPInt().countTrailingZeros();
+ return cast<SCEVConstant>(S)->getAPInt().countr_zero();
case scTruncate: {
const SCEVTruncateExpr *T = cast<SCEVTruncateExpr>(S);
return std::min(GetMinTrailingZeros(T->getOperand()),
@@ -7762,8 +7762,8 @@ const SCEV *ScalarEvolution::createSCEV(Value *V) {
// constants, obscuring what would otherwise be a low-bits mask.
// Use computeKnownBits to compute what ShrinkDemandedConstant
// knew about to reconstruct a low-bits mask value.
- unsigned LZ = A.countLeadingZeros();
- unsigned TZ = A.countTrailingZeros();
+ unsigned LZ = A.countl_zero();
+ unsigned TZ = A.countr_zero();
unsigned BitWidth = A.getBitWidth();
KnownBits Known(BitWidth);
computeKnownBits(BO->LHS, Known, getDataLayout(),
@@ -7778,7 +7778,7 @@ const SCEV *ScalarEvolution::createSCEV(Value *V) {
if (auto *LHSMul = dyn_cast<SCEVMulExpr>(LHS)) {
if (auto *OpC = dyn_cast<SCEVConstant>(LHSMul->getOperand(0))) {
// For an expression like (x * 8) & 8, simplify the multiply.
- unsigned MulZeros = OpC->getAPInt().countTrailingZeros();
+ unsigned MulZeros = OpC->getAPInt().countr_zero();
unsigned GCD = std::min(MulZeros, TZ);
APInt DivAmt = APInt::getOneBitSet(BitWidth, TZ - GCD);
SmallVector<const SCEV*, 4> MulOps;
@@ -10108,7 +10108,7 @@ static const SCEV *SolveLinEquationWithOverflow(const APInt &A, const SCEV *B,
//
// The gcd of A and N may have only one prime factor: 2. The number of
// trailing zeros in A is its multiplicity
- uint32_t Mult2 = A.countTrailingZeros();
+ uint32_t Mult2 = A.countr_zero();
// D = 2^Mult2
// 2. Check if B is divisible by D.
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index bf3b4c94249d0..5bd8cacd8aa7c 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -479,7 +479,7 @@ void llvm::computeKnownBitsFromRangeMetadata(const MDNode &Ranges,
// The first CommonPrefixBits of all values in Range are equal.
unsigned CommonPrefixBits =
- (Range.getUnsignedMax() ^ Range.getUnsignedMin()).countLeadingZeros();
+ (Range.getUnsignedMax() ^ Range.getUnsignedMin()).countl_zero();
APInt Mask = APInt::getHighBitsSet(BitWidth, CommonPrefixBits);
APInt UnsignedMax = Range.getUnsignedMax().zextOrTrunc(BitWidth);
Known.One &= UnsignedMax & Mask;
@@ -1301,7 +1301,7 @@ static void computeKnownBitsFromOperator(const Operator *I,
// Trailing zeros of a right-shifted constant never decrease.
const APInt *C;
if (match(I->getOperand(0), m_APInt(C)))
- Known.Zero.setLowBits(C->countTrailingZeros());
+ Known.Zero.setLowBits(C->countr_zero());
break;
}
case Instruction::LShr: {
@@ -1313,7 +1313,7 @@ static void computeKnownBitsFromOperator(const Operator *I,
// Leading zeros of a left-shifted constant never decrease.
const APInt *C;
if (match(I->getOperand(0), m_APInt(C)))
- Known.Zero.setHighBits(C->countLeadingZeros());
+ Known.Zero.setHighBits(C->countl_zero());
break;
}
case Instruction::AShr: {
@@ -1601,10 +1601,10 @@ static void computeKnownBitsFromOperator(const Operator *I,
Known2 = KnownBits::makeConstant(*RHSC);
break;
case CmpInst::Predicate::ICMP_ULE:
- Known2.Zero.setHighBits(RHSC->countLeadingZeros());
+ Known2.Zero.setHighBits(RHSC->countl_zero());
break;
case CmpInst::Predicate::ICMP_ULT:
- Known2.Zero.setHighBits((*RHSC - 1).countLeadingZeros());
+ Known2.Zero.setHighBits((*RHSC - 1).countl_zero());
break;
default:
// TODO - add additional integer predicate handling.
@@ -7171,7 +7171,7 @@ static void setLimitsForBinOp(const BinaryOperator &BO, APInt &Lower,
} else if (match(BO.getOperand(0), m_APInt(C))) {
unsigned ShiftAmount = Width - 1;
if (!C->isZero() && IIQ.isExact(&BO))
- ShiftAmount = C->countTrailingZeros();
+ ShiftAmount = C->countr_zero();
if (C->isNegative()) {
// 'ashr C, x' produces [C, C >> (Width-1)]
Lower = *C;
@@ -7192,7 +7192,7 @@ static void setLimitsForBinOp(const BinaryOperator &BO, APInt &Lower,
// 'lshr C, x' produces [C >> (Width-1), C].
unsigned ShiftAmount = Width - 1;
if (!C->isZero() && IIQ.isExact(&BO))
- ShiftAmount = C->countTrailingZeros();
+ ShiftAmount = C->countr_zero();
Lower = C->lshr(ShiftAmount);
Upper = *C + 1;
}
@@ -7203,16 +7203,16 @@ static void setLimitsForBinOp(const BinaryOperator &BO, APInt &Lower,
if (IIQ.hasNoUnsignedWrap(&BO)) {
// 'shl nuw C, x' produces [C, C << CLZ(C)]
Lower = *C;
- Upper = Lower.shl(Lower.countLeadingZeros()) + 1;
+ Upper = Lower.shl(Lower.countl_zero()) + 1;
} else if (BO.hasNoSignedWrap()) { // TODO: What if both nuw+nsw?
if (C->isNegative()) {
// 'shl nsw C, x' produces [C << CLO(C)-1, C]
- unsigned ShiftAmount = C->countLeadingOnes() - 1;
+ unsigned ShiftAmount = C->countl_one() - 1;
Lower = C->shl(ShiftAmount);
Upper = *C + 1;
} else {
// 'shl nsw C, x' produces [C, C << CLZ(C)-1]
- unsigned ShiftAmount = C->countLeadingZeros() - 1;
+ unsigned ShiftAmount = C->countl_zero() - 1;
Lower = *C;
Upper = C->shl(ShiftAmount) + 1;
}
@@ -7229,7 +7229,7 @@ static void setLimitsForBinOp(const BinaryOperator &BO, APInt &Lower,
// where C != -1 and C != 0 and C != 1
Lower = IntMin + 1;
Upper = IntMax + 1;
- } else if (C->countLeadingZeros() < Width - 1) {
+ } else if (C->countl_zero() < Width - 1) {
// 'sdiv x, C' produces [INT_MIN / C, INT_MAX / C]
// where C != -1 and C != 0 and C != 1
Lower = IntMin.sdiv(*C);
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index ec4e45ed0d951..5b7b5615cf401 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -730,7 +730,7 @@ bool CombinerHelper::matchCombineLoadWithAndMask(MachineInstr &MI,
Register PtrReg = LoadMI->getPointerReg();
unsigned RegSize = RegTy.getSizeInBits();
uint64_t LoadSizeBits = LoadMI->getMemSizeInBits();
- unsigned MaskSizeBits = MaskVal.countTrailingOnes();
+ unsigned MaskSizeBits = MaskVal.countr_one();
// The mask may not be larger than the in-memory type, as it might cover sign
// extended bits
@@ -1682,7 +1682,7 @@ bool CombinerHelper::matchCombineShlOfExtend(MachineInstr &MI,
MatchData.Reg = ExtSrc;
MatchData.Imm = ShiftAmt;
- unsigned MinLeadingZeros = KB->getKnownZeroes(ExtSrc).countLeadingOnes();
+ unsigned MinLeadingZeros = KB->getKnownZeroes(ExtSrc).countl_one();
return MinLeadingZeros >= ShiftAmt;
}
@@ -4407,7 +4407,7 @@ bool CombinerHelper::matchBitfieldExtractFromAnd(
if (static_cast<uint64_t>(LSBImm) >= Size)
return false;
- uint64_t Width = APInt(Size, AndImm).countTrailingOnes();
+ uint64_t Width = APInt(Size, AndImm).countr_one();
MatchInfo = [=](MachineIRBuilder &B) {
auto WidthCst = B.buildConstant(ExtractTy, Width);
auto LSBCst = B.buildConstant(ExtractTy, LSBImm);
@@ -4778,7 +4778,7 @@ bool CombinerHelper::matchNarrowBinopFeedingAnd(
return false;
// No point in combining if there's nothing to truncate.
- unsigned NarrowWidth = Mask.countTrailingOnes();
+ unsigned NarrowWidth = Mask.countr_one();
if (NarrowWidth == WideTy.getSizeInBits())
return false;
LLT NarrowTy = LLT::scalar(NarrowWidth);
@@ -5156,7 +5156,7 @@ MachineInstr *CombinerHelper::buildSDivUsingMul(MachineInstr &MI) {
auto *CI = cast<ConstantInt>(C);
APInt Divisor = CI->getValue();
- unsigned Shift = Divisor.countTrailingZeros();
+ unsigned Shift = Divisor.countr_zero();
if (Shift) {
Divisor.ashrInPlace(Shift);
UseSRA = true;
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index bfbe7e1c3e557..a33d59079acc8 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -750,7 +750,7 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
// Okay, we know that the sign bit in Mask is set. Use CLO to determine
// the number of identical bits in the top of the input value.
Mask <<= Mask.getBitWidth() - TyBits;
- return std::max(FirstAnswer, Mask.countLeadingOnes());
+ return std::max(FirstAnswer, Mask.countl_one());
}
unsigned GISelKnownBits::computeNumSignBits(Register R, unsigned Depth) {
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 07448548c2952..641160f36587e 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -797,7 +797,7 @@ llvm::ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI) {
auto MaybeCst = getIConstantVRegVal(R, MRI);
if (!MaybeCst)
return std::nullopt;
- return MaybeCst->countLeadingZeros();
+ return MaybeCst->countl_zero();
};
if (Ty.isVector()) {
// Try to constant fold each element.
diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
index 0d36badfa10f7..4154cd88e934a 100644
--- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
+++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
@@ -318,7 +318,7 @@ class Polynomial {
// See Proof(2): Trailing zero bits indicate a left shift. This removes
// leading bits from the result even if they are undefined.
- decErrorMSBs(C.countTrailingZeros());
+ decErrorMSBs(C.countr_zero());
A *= C;
pushBOperation(Mul, C);
@@ -475,7 +475,7 @@ class Polynomial {
//
// If this can be proven add shiftAmt to the error counter
// `ErrorMSBs`. Otherwise set all bits as undefined.
- if (A.countTrailingZeros() < shiftAmt)
+ if (A.countr_zero() < shiftAmt)
ErrorMSBs = A.getBitWidth();
else
incErrorMSBs(shiftAmt);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7a1520cf6967e..f8fd1cefb9b98 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4275,7 +4275,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
unsigned MathOp = ISD::DELETED_NODE;
APInt MulC = ConstValue1.abs();
// The constant `2` should be treated as (2^0 + 1).
- unsigned TZeros = MulC == 2 ? 0 : MulC.countTrailingZeros();
+ unsigned TZeros = MulC == 2 ? 0 : MulC.countr_zero();
MulC.lshrInPlace(TZeros);
if ((MulC - 1).isPowerOf2())
MathOp = ISD::ADD;
@@ -6024,7 +6024,7 @@ SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
if (ShiftBits == 0)
return SDValue();
- unsigned MaskBits = AndMask.countTrailingOnes();
+ unsigned MaskBits = AndMask.countr_one();
EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
if (AndMask.isMask() &&
@@ -6067,7 +6067,7 @@ bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
if (!AndC->getAPIntValue().isMask())
return false;
- unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();
+ unsigned ActiveBits = AndC->getAPIntValue().countr_one();
ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
EVT LoadedVT = LoadN->getMemoryVT();
@@ -6231,7 +6231,7 @@ bool DAGCombiner::SearchForAndLoads(SDNode *N,
}
case ISD::ZERO_EXTEND:
case ISD::AssertZext: {
- unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
+ unsigned ActiveBits = Mask->getAPIntValue().countr_one();
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
EVT VT = Op.getOpcode() == ISD::AssertZext ?
cast<VTSDNode>(Op.getOperand(1))->getVT() :
@@ -10266,7 +10266,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
// could be set on input to the CTLZ node. If this bit is set, the SRL
// will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
// to an SRL/XOR pair, which is likely to simplify more.
- unsigned ShAmt = UnknownBits.countTrailingZeros();
+ unsigned ShAmt = UnknownBits.countr_zero();
SDValue Op = N0.getOperand(0);
if (ShAmt) {
@@ -13753,7 +13753,7 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
const APInt &Mask = AndC->getAPIntValue();
unsigned ActiveBits = 0;
if (Mask.isMask()) {
- ActiveBits = Mask.countTrailingOnes();
+ ActiveBits = Mask.countr_one();
} else if (Mask.isShiftedMask(ShAmt, ActiveBits)) {
HasShiftedOffset = true;
} else {
@@ -13821,8 +13821,8 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
isa<ConstantSDNode>(Mask->getOperand(1))) {
const APInt& ShiftMask = Mask->getConstantOperandAPInt(1);
if (ShiftMask.isMask()) {
- EVT MaskedVT = EVT::getIntegerVT(*DAG.getContext(),
- ShiftMask.countTrailingOnes());
+ EVT MaskedVT =
+ EVT::getIntegerVT(*DAG.getContext(), ShiftMask.countr_one());
// If the mask is smaller, recompute the type.
if ((ExtVT.getScalarSizeInBits() > MaskedVT.getScalarSizeInBits()) &&
TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT))
@@ -18372,9 +18372,9 @@ static bool areUsedBitsDense(const APInt &UsedBits) {
return true;
// Get rid of the unused bits on the right.
- APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
+ APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countr_zero());
// Get rid of the unused bits on the left.
- if (NarrowedUsedBits.countLeadingZeros())
+ if (NarrowedUsedBits.countl_zero())
NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
// Check that the chunk of bits is completely used.
return NarrowedUsedBits.isAllOnes();
@@ -18814,8 +18814,8 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
Imm ^= APInt::getAllOnes(BitWidth);
if (Imm == 0 || Imm.isAllOnes())
return SDValue();
- unsigned ShAmt = Imm.countTrailingZeros();
- unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
+ unsigned ShAmt = Imm.countr_zero();
+ unsigned MSB = BitWidth - Imm.countl_zero() - 1;
unsigned NewBW = NextPowerOf2(MSB - ShAmt);
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
// The narrowing should be profitable, the load/store operation should be
@@ -26115,8 +26115,8 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
unsigned ShCt = AndMask.getBitWidth() - 1;
if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) {
SDValue ShlAmt =
- DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS),
- getShiftAmountTy(AndLHS.getValueType()));
+ DAG.getConstant(AndMask.countl_zero(), SDLoc(AndLHS),
+ getShiftAmountTy(AndLHS.getValueType()));
SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
// Now arithmetic right shift it all the way over, so the result is
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 457901099018b..1e777aee0b81f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -200,10 +200,10 @@ bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) {
SDValue NotZero = N->getOperand(i);
unsigned EltSize = N->getValueType(0).getScalarSizeInBits();
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(NotZero)) {
- if (CN->getAPIntValue().countTrailingOnes() < EltSize)
+ if (CN->getAPIntValue().countr_one() < EltSize)
return false;
} else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(NotZero)) {
- if (CFPN->getValueAPF().bitcastToAPInt().countTrailingOnes() < EltSize)
+ if (CFPN->getValueAPF().bitcastToAPInt().countr_one() < EltSize)
return false;
} else
return false;
@@ -244,10 +244,10 @@ bool ISD::isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly) {
// constants are.
unsigned EltSize = N->getValueType(0).getScalarSizeInBits();
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op)) {
- if (CN->getAPIntValue().countTrailingZeros() < EltSize)
+ if (CN->getAPIntValue().countr_zero() < EltSize)
return false;
} else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(Op)) {
- if (CFPN->getValueAPF().bitcastToAPInt().countTrailingZeros() < EltSize)
+ if (CFPN->getValueAPF().bitcastToAPInt().countr_zero() < EltSize)
return false;
} else
return false;
@@ -2833,7 +2833,7 @@ SDValue SelectionDAG::getSplatSourceVector(SDValue V, int &SplatIdx) {
SplatIdx = 0;
return getUNDEF(VT);
}
- SplatIdx = (UndefElts & DemandedElts).countTrailingOnes();
+ SplatIdx = (UndefElts & DemandedElts).countr_one();
}
return V;
}
@@ -5268,11 +5268,11 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
C->isOpaque());
case ISD::CTLZ:
case ISD::CTLZ_ZERO_UNDEF:
- return getConstant(Val.countLeadingZeros(), DL, VT, C->isTargetOpcode(),
+ return getConstant(Val.countl_zero(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::CTTZ:
case ISD::CTTZ_ZERO_UNDEF:
- return getConstant(Val.countTrailingZeros(), DL, VT, C->isTargetOpcode(),
+ return getConstant(Val.countr_zero(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::FP16_TO_FP:
case ISD::BF16_TO_FP: {
@@ -11025,7 +11025,7 @@ bool llvm::isBitwiseNot(SDValue V, bool AllowUndefs) {
unsigned NumBits = V.getScalarValueSizeInBits();
ConstantSDNode *C =
isConstOrConstSplat(V, AllowUndefs, /*AllowTruncation*/ true);
- return C && (C->getAPIntValue().countTrailingOnes() >= NumBits);
+ return C && (C->getAPIntValue().countr_one() >= NumBits);
}
ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, bool AllowUndefs,
@@ -11829,7 +11829,7 @@ SDValue BuildVectorSDNode::getSplatValue(const APInt &DemandedElts,
}
if (!Splatted) {
- unsigned FirstDemandedIdx = DemandedElts.countTrailingZeros();
+ unsigned FirstDemandedIdx = DemandedElts.countr_zero();
assert(getOperand(FirstDemandedIdx).isUndef() &&
"Can only have a splat without a constant for all undefs.");
return getOperand(FirstDemandedIdx);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 25d4223eafecf..d5fae603cb3c5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -772,7 +772,7 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
unsigned ShAmt = MaxSA->getZExtValue();
unsigned NumSignBits =
DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
- unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros();
+ unsigned UpperDemandedBits = BitWidth - DemandedBits.countr_zero();
if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits))
return Op0;
}
@@ -1745,7 +1745,7 @@ bool TargetLowering::SimplifyDemandedBits(
if (InnerShAmt < ShAmt && InnerShAmt < InnerBits &&
DemandedBits.getActiveBits() <=
(InnerBits - InnerShAmt + ShAmt) &&
- DemandedBits.countTrailingZeros() >= ShAmt) {
+ DemandedBits.countr_zero() >= ShAmt) {
SDValue NewSA =
TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, ShiftVT);
SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
@@ -1786,7 +1786,7 @@ bool TargetLowering::SimplifyDemandedBits(
// This is a variable shift, so we can't shift the demand mask by a known
// amount. But if we are not demanding high bits, then we are not
// demanding those bits from the pre-shifted operand either.
- if (unsigned CTLZ = DemandedBits.countLeadingZeros()) {
+ if (unsigned CTLZ = DemandedBits.countl_zero()) {
APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ));
if (SimplifyDemandedBits(Op0, DemandedFromOp, DemandedElts, Known, TLO,
Depth + 1)) {
@@ -1811,7 +1811,7 @@ bool TargetLowering::SimplifyDemandedBits(
unsigned ShAmt = MaxSA->getZExtValue();
unsigned NumSignBits =
TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
- unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros();
+ unsigned UpperDemandedBits = BitWidth - DemandedBits.countr_zero();
if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits))
return TLO.CombineTo(Op, Op0);
}
@@ -1891,7 +1891,7 @@ bool TargetLowering::SimplifyDemandedBits(
// If we only want bits that already match the signbit then we don't need
// to shift.
- unsigned NumHiDemandedBits = BitWidth - DemandedBits.countTrailingZeros();
+ unsigned NumHiDemandedBits = BitWidth - DemandedBits.countr_zero();
if (TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >=
NumHiDemandedBits)
return TLO.CombineTo(Op, Op0);
@@ -1923,7 +1923,7 @@ bool TargetLowering::SimplifyDemandedBits(
// If any of the demanded bits are produced by the sign extension, we also
// demand the input sign bit.
- if (DemandedBits.countLeadingZeros() < ShAmt)
+ if (DemandedBits.countl_zero() < ShAmt)
InDemandedMask.setSignBit();
if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
@@ -1936,7 +1936,7 @@ bool TargetLowering::SimplifyDemandedBits(
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
if (Known.Zero[BitWidth - ShAmt - 1] ||
- DemandedBits.countLeadingZeros() >= ShAmt) {
+ DemandedBits.countl_zero() >= ShAmt) {
SDNodeFlags Flags;
Flags.setExact(Op->getFlags().hasExact());
return TLO.CombineTo(
@@ -2056,12 +2056,12 @@ bool TargetLowering::SimplifyDemandedBits(
// See if we don't demand either half of the rotated bits.
if ((!TLO.LegalOperations() || isOperationLegal(ISD::SHL, VT)) &&
- DemandedBits.countTrailingZeros() >= (IsROTL ? Amt : RevAmt)) {
+ DemandedBits.countr_zero() >= (IsROTL ? Amt : RevAmt)) {
Op1 = TLO.DAG.getConstant(IsROTL ? Amt : RevAmt, dl, Op1.getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, Op1));
}
if ((!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) &&
- DemandedBits.countLeadingZeros() >= (IsROTL ? RevAmt : Amt)) {
+ DemandedBits.countl_zero() >= (IsROTL ? RevAmt : Amt)) {
Op1 = TLO.DAG.getConstant(IsROTL ? RevAmt : Amt, dl, Op1.getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
}
@@ -2117,8 +2117,8 @@ bool TargetLowering::SimplifyDemandedBits(
// If the only bits demanded come from one byte of the bswap result,
// just shift the input byte into position to eliminate the bswap.
- unsigned NLZ = DemandedBits.countLeadingZeros();
- unsigned NTZ = DemandedBits.countTrailingZeros();
+ unsigned NLZ = DemandedBits.countl_zero();
+ unsigned NTZ = DemandedBits.countr_zero();
// Round NTZ down to the next byte. If we have 11 trailing zeros, then
// we need all the bits down to bit 8. Likewise, round NLZ. If we
@@ -2569,9 +2569,9 @@ bool TargetLowering::SimplifyDemandedBits(
// The LSB of X*Y is set only if (X & 1) == 1 and (Y & 1) == 1.
// If we demand exactly one bit N and we have "X * (C' << N)" where C' is
// odd (has LSB set), then the left-shifted low bit of X is the answer.
- unsigned CTZ = DemandedBits.countTrailingZeros();
+ unsigned CTZ = DemandedBits.countr_zero();
ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1), DemandedElts);
- if (C && C->getAPIntValue().countTrailingZeros() == CTZ) {
+ if (C && C->getAPIntValue().countr_zero() == CTZ) {
EVT ShiftAmtTy = getShiftAmountTy(VT, TLO.DAG.getDataLayout());
SDValue AmtC = TLO.DAG.getConstant(CTZ, dl, ShiftAmtTy);
SDValue Shl = TLO.DAG.getNode(ISD::SHL, dl, VT, Op.getOperand(0), AmtC);
@@ -2593,7 +2593,7 @@ bool TargetLowering::SimplifyDemandedBits(
// of the highest bit demanded of them.
SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
SDNodeFlags Flags = Op.getNode()->getFlags();
- unsigned DemandedBitsLZ = DemandedBits.countLeadingZeros();
+ unsigned DemandedBitsLZ = DemandedBits.countl_zero();
APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ);
if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO,
Depth + 1) ||
@@ -4312,7 +4312,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// DAGCombine turns costly ZExts into ANDs
if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
if ((C->getAPIntValue()+1).isPowerOf2()) {
- MinBits = C->getAPIntValue().countTrailingOnes();
+ MinBits = C->getAPIntValue().countr_one();
PreExt = N0->getOperand(0);
}
} else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
@@ -4872,7 +4872,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
const APInt &AndRHSC = AndRHS->getAPIntValue();
if (AndRHSC.isNegatedPowerOf2() && (AndRHSC & C1) == C1) {
- unsigned ShiftBits = AndRHSC.countTrailingZeros();
+ unsigned ShiftBits = AndRHSC.countr_zero();
if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
SDValue Shift =
DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0),
@@ -4893,11 +4893,11 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
APInt NewC = C1;
ISD::CondCode NewCond = Cond;
if (AdjOne) {
- ShiftBits = C1.countTrailingOnes();
+ ShiftBits = C1.countr_one();
NewC = NewC + 1;
NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
} else {
- ShiftBits = C1.countTrailingZeros();
+ ShiftBits = C1.countr_zero();
}
NewC.lshrInPlace(ShiftBits);
if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
@@ -5779,7 +5779,7 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
if (C->isZero())
return false;
APInt Divisor = C->getAPIntValue();
- unsigned Shift = Divisor.countTrailingZeros();
+ unsigned Shift = Divisor.countr_zero();
if (Shift) {
Divisor.ashrInPlace(Shift);
UseSRA = true;
@@ -6042,9 +6042,8 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
LeadingZeros = DAG.computeKnownBits(N0).countMinLeadingZeros();
// UnsignedDivisionByConstantInfo doesn't work correctly if leading zeros in
// the dividend exceeds the leading zeros for the divisor.
- LeadingZeros =
- std::min(LeadingZeros,
- cast<ConstantSDNode>(N1)->getAPIntValue().countLeadingZeros());
+ LeadingZeros = std::min(
+ LeadingZeros, cast<ConstantSDNode>(N1)->getAPIntValue().countl_zero());
}
bool UseNPQ = false, UsePreShift = false, UsePostShift = false;
@@ -6295,7 +6294,7 @@ TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
AllComparisonsWithNonZerosAreTautological &= TautologicalLane;
// Decompose D into D0 * 2^K
- unsigned K = D.countTrailingZeros();
+ unsigned K = D.countr_zero();
assert((!D.isOne() || (K == 0)) && "For divisor '1' we won't rotate.");
APInt D0 = D.lshr(K);
@@ -6537,7 +6536,7 @@ TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
AllDivisorsAreOnes &= D.isOne();
// Decompose D into D0 * 2^K
- unsigned K = D.countTrailingZeros();
+ unsigned K = D.countr_zero();
assert((!D.isOne() || (K == 0)) && "For divisor '1' we won't rotate.");
APInt D0 = D.lshr(K);
@@ -7327,7 +7326,7 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
// If the divisor is even, shift it until it becomes odd.
unsigned TrailingZeros = 0;
if (!Divisor[0]) {
- TrailingZeros = Divisor.countTrailingZeros();
+ TrailingZeros = Divisor.countr_zero();
Divisor.lshrInPlace(TrailingZeros);
}
diff --git a/llvm/lib/IR/ConstantRange.cpp b/llvm/lib/IR/ConstantRange.cpp
index ab94053df45a1..af70bfe1ec12a 100644
--- a/llvm/lib/IR/ConstantRange.cpp
+++ b/llvm/lib/IR/ConstantRange.cpp
@@ -816,8 +816,7 @@ ConstantRange ConstantRange::truncate(uint32_t DstTySize) const {
if (isUpperWrapped()) {
// If Upper is greater than or equal to MaxValue(DstTy), it covers the whole
// truncated range.
- if (Upper.getActiveBits() > DstTySize ||
- Upper.countTrailingOnes() == DstTySize)
+ if (Upper.getActiveBits() > DstTySize || Upper.countr_one() == DstTySize)
return getFull(DstTySize);
Union = ConstantRange(APInt::getMaxValue(DstTySize),Upper.trunc(DstTySize));
@@ -1455,7 +1454,7 @@ ConstantRange::shl(const ConstantRange &Other) const {
if (RHS->uge(BW))
return getEmpty();
- unsigned EqualLeadingBits = (Min ^ Max).countLeadingZeros();
+ unsigned EqualLeadingBits = (Min ^ Max).countl_zero();
if (RHS->ule(EqualLeadingBits))
return getNonEmpty(Min << *RHS, (Max << *RHS) + 1);
@@ -1466,7 +1465,7 @@ ConstantRange::shl(const ConstantRange &Other) const {
APInt OtherMax = Other.getUnsignedMax();
// There's overflow!
- if (OtherMax.ugt(Max.countLeadingZeros()))
+ if (OtherMax.ugt(Max.countl_zero()))
return getFull();
// FIXME: implement the other tricky cases
@@ -1695,12 +1694,12 @@ ConstantRange ConstantRange::ctlz(bool ZeroIsPoison) const {
// Compute the resulting range by excluding zero from Lower.
return ConstantRange(
- APInt(getBitWidth(), (getUpper() - 1).countLeadingZeros()),
- APInt(getBitWidth(), (getLower() + 1).countLeadingZeros() + 1));
+ APInt(getBitWidth(), (getUpper() - 1).countl_zero()),
+ APInt(getBitWidth(), (getLower() + 1).countl_zero() + 1));
} else if ((getUpper() - 1).isZero()) {
// Compute the resulting range by excluding zero from Upper.
- return ConstantRange(
- Zero, APInt(getBitWidth(), getLower().countLeadingZeros() + 1));
+ return ConstantRange(Zero,
+ APInt(getBitWidth(), getLower().countl_zero() + 1));
} else {
return ConstantRange(Zero, APInt(getBitWidth(), getBitWidth()));
}
@@ -1708,9 +1707,8 @@ ConstantRange ConstantRange::ctlz(bool ZeroIsPoison) const {
// Zero is either safe or not in the range. The output range is composed by
// the result of countLeadingZero of the two extremes.
- return getNonEmpty(
- APInt(getBitWidth(), getUnsignedMax().countLeadingZeros()),
- APInt(getBitWidth(), getUnsignedMin().countLeadingZeros() + 1));
+ return getNonEmpty(APInt(getBitWidth(), getUnsignedMax().countl_zero()),
+ APInt(getBitWidth(), getUnsignedMin().countl_zero() + 1));
}
ConstantRange::OverflowResult ConstantRange::unsignedAddMayOverflow(
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 7c343a0ff00a1..3746a3de7eed3 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -2501,10 +2501,10 @@ bool ShuffleVectorInst::isInsertSubvectorMask(ArrayRef<int> Mask,
// Determine lo/hi span ranges.
// TODO: How should we handle undefs at the start of subvector insertions?
- int Src0Lo = Src0Elts.countTrailingZeros();
- int Src1Lo = Src1Elts.countTrailingZeros();
- int Src0Hi = NumMaskElts - Src0Elts.countLeadingZeros();
- int Src1Hi = NumMaskElts - Src1Elts.countLeadingZeros();
+ int Src0Lo = Src0Elts.countr_zero();
+ int Src1Lo = Src1Elts.countr_zero();
+ int Src0Hi = NumMaskElts - Src0Elts.countl_zero();
+ int Src1Hi = NumMaskElts - Src1Elts.countl_zero();
// If src0 is in place, see if the src1 elements is inplace within its own
// span.
diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp
index fa22065dcf364..1a7ee3169da03 100644
--- a/llvm/lib/IR/Value.cpp
+++ b/llvm/lib/IR/Value.cpp
@@ -972,7 +972,7 @@ Align Value::getPointerAlignment(const DataLayout &DL) const {
if (auto *CstInt = dyn_cast_or_null<ConstantInt>(ConstantExpr::getPtrToInt(
const_cast<Constant *>(CstPtr), DL.getIntPtrType(getType()),
/*OnlyIfReduced=*/true))) {
- size_t TrailingZeros = CstInt->getValue().countTrailingZeros();
+ size_t TrailingZeros = CstInt->getValue().countr_zero();
// While the actual alignment may be large, elsewhere we have
// an arbitrary upper alignmet limit, so let's clamp to it.
return Align(TrailingZeros < Value::MaxAlignmentExponent
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 9cdd9b0a35296..fdf16f6fa964d 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -4312,7 +4312,7 @@ void IEEEFloat::toString(SmallVectorImpl<char> &Str, unsigned FormatPrecision,
}
// Ignore trailing binary zeros.
- int trailingZeros = significand.countTrailingZeros();
+ int trailingZeros = significand.countr_zero();
exp += trailingZeros;
significand.lshrInPlace(trailingZeros);
diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp
index 857d400596b11..e10057d76d6e0 100644
--- a/llvm/lib/Support/APInt.cpp
+++ b/llvm/lib/Support/APInt.cpp
@@ -767,8 +767,8 @@ APInt llvm::APIntOps::GreatestCommonDivisor(APInt A, APInt B) {
// Count common powers of 2 and remove all other powers of 2.
unsigned Pow2;
{
- unsigned Pow2_A = A.countTrailingZeros();
- unsigned Pow2_B = B.countTrailingZeros();
+ unsigned Pow2_A = A.countr_zero();
+ unsigned Pow2_B = B.countr_zero();
if (Pow2_A > Pow2_B) {
A.lshrInPlace(Pow2_A - Pow2_B);
Pow2 = Pow2_B;
@@ -789,10 +789,10 @@ APInt llvm::APIntOps::GreatestCommonDivisor(APInt A, APInt B) {
while (A != B) {
if (A.ugt(B)) {
A -= B;
- A.lshrInPlace(A.countTrailingZeros() - Pow2);
+ A.lshrInPlace(A.countr_zero() - Pow2);
} else {
B -= A;
- B.lshrInPlace(B.countTrailingZeros() - Pow2);
+ B.lshrInPlace(B.countr_zero() - Pow2);
}
}
@@ -1967,7 +1967,7 @@ APInt APInt::smul_ov(const APInt &RHS, bool &Overflow) const {
}
APInt APInt::umul_ov(const APInt &RHS, bool &Overflow) const {
- if (countLeadingZeros() + RHS.countLeadingZeros() + 2 <= BitWidth) {
+ if (countl_zero() + RHS.countl_zero() + 2 <= BitWidth) {
Overflow = true;
return *this * RHS;
}
@@ -1989,9 +1989,9 @@ APInt APInt::sshl_ov(const APInt &ShAmt, bool &Overflow) const {
return APInt(BitWidth, 0);
if (isNonNegative()) // Don't allow sign change.
- Overflow = ShAmt.uge(countLeadingZeros());
+ Overflow = ShAmt.uge(countl_zero());
else
- Overflow = ShAmt.uge(countLeadingOnes());
+ Overflow = ShAmt.uge(countl_one());
return *this << ShAmt;
}
@@ -2001,7 +2001,7 @@ APInt APInt::ushl_ov(const APInt &ShAmt, bool &Overflow) const {
if (Overflow)
return APInt(BitWidth, 0);
- Overflow = ShAmt.ugt(countLeadingZeros());
+ Overflow = ShAmt.ugt(countl_zero());
return *this << ShAmt;
}
@@ -2954,7 +2954,7 @@ llvm::APIntOps::GetMostSignificantDifferentBit(const APInt &A, const APInt &B) {
assert(A.getBitWidth() == B.getBitWidth() && "Must have the same bitwidth");
if (A == B)
return std::nullopt;
- return A.getBitWidth() - ((A ^ B).countLeadingZeros() + 1);
+ return A.getBitWidth() - ((A ^ B).countl_zero() + 1);
}
APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth,
diff --git a/llvm/lib/Support/DivisionByConstantInfo.cpp b/llvm/lib/Support/DivisionByConstantInfo.cpp
index e7072d94e49ce..8150bd83c79f4 100644
--- a/llvm/lib/Support/DivisionByConstantInfo.cpp
+++ b/llvm/lib/Support/DivisionByConstantInfo.cpp
@@ -132,7 +132,7 @@ UnsignedDivisionByConstantInfo::get(const APInt &D, unsigned LeadingZeros,
(Q1.ult(Delta) || (Q1 == Delta && R1.isZero())));
if (Retval.IsAdd && !D[0] && AllowEvenDivisorOptimization) {
- unsigned PreShift = D.countTrailingZeros();
+ unsigned PreShift = D.countr_zero();
APInt ShiftedD = D.lshr(PreShift);
Retval =
UnsignedDivisionByConstantInfo::get(ShiftedD, LeadingZeros + PreShift);
diff --git a/llvm/lib/Support/KnownBits.cpp b/llvm/lib/Support/KnownBits.cpp
index cb6f5082d6aff..8b0d6030fea32 100644
--- a/llvm/lib/Support/KnownBits.cpp
+++ b/llvm/lib/Support/KnownBits.cpp
@@ -105,7 +105,7 @@ KnownBits KnownBits::sextInReg(unsigned SrcBitWidth) const {
KnownBits KnownBits::makeGE(const APInt &Val) const {
// Count the number of leading bit positions where our underlying value is
// known to be less than or equal to Val.
- unsigned N = (Zero | Val).countLeadingOnes();
+ unsigned N = (Zero | Val).countl_one();
// For each of those bit positions, if Val has a 1 in that bit then our
// underlying value must also have a 1.
@@ -432,7 +432,7 @@ KnownBits KnownBits::mul(const KnownBits &LHS, const KnownBits &RHS,
// fit in the bitwidth (it must not overflow).
bool HasOverflow;
APInt UMaxResult = UMaxLHS.umul_ov(UMaxRHS, HasOverflow);
- unsigned LeadZ = HasOverflow ? 0 : UMaxResult.countLeadingZeros();
+ unsigned LeadZ = HasOverflow ? 0 : UMaxResult.countl_zero();
// The result of the bottom bits of an integer multiply can be
// inferred by looking at the bottom bits of both operands and
@@ -481,8 +481,8 @@ KnownBits KnownBits::mul(const KnownBits &LHS, const KnownBits &RHS,
// How many times we'd be able to divide each argument by 2 (shr by 1).
// This gives us the number of trailing zeros on the multiplication result.
- unsigned TrailBitsKnown0 = (LHS.Zero | LHS.One).countTrailingOnes();
- unsigned TrailBitsKnown1 = (RHS.Zero | RHS.One).countTrailingOnes();
+ unsigned TrailBitsKnown0 = (LHS.Zero | LHS.One).countr_one();
+ unsigned TrailBitsKnown1 = (RHS.Zero | RHS.One).countr_one();
unsigned TrailZero0 = LHS.countMinTrailingZeros();
unsigned TrailZero1 = RHS.countMinTrailingZeros();
unsigned TrailZ = TrailZero0 + TrailZero1;
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index 41f9303da1bf5..8575aacf78ff7 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -4848,7 +4848,7 @@ bool AArch64FastISel::selectSDiv(const Instruction *I) {
!(C.isPowerOf2() || C.isNegatedPowerOf2()))
return selectBinaryOp(I, ISD::SDIV);
- unsigned Lg2 = C.countTrailingZeros();
+ unsigned Lg2 = C.countr_zero();
Register Src0Reg = getRegForValue(I->getOperand(0));
if (!Src0Reg)
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index de31715f5d878..2be404bb7441f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -3378,8 +3378,8 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
// Because of simplify-demanded-bits in DAGCombine, involved masks may not
// have the expected shape. Try to undo that.
- unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
- unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();
+ unsigned NumberOfIgnoredLowBits = UsefulBits.countr_zero();
+ unsigned NumberOfIgnoredHighBits = UsefulBits.countl_zero();
// Given a OR operation, check if we have the following pattern
// ubfm c, b, imm, imm2 (or something that does the same jobs, see
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8e6180a2b2764..73a9c14ab9734 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15391,7 +15391,7 @@ AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
SDLoc DL(N);
SDValue N0 = N->getOperand(0);
- unsigned Lg2 = Divisor.countTrailingZeros();
+ unsigned Lg2 = Divisor.countr_zero();
SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
@@ -15438,7 +15438,7 @@ AArch64TargetLowering::BuildSREMPow2(SDNode *N, const APInt &Divisor,
!(Divisor.isPowerOf2() || Divisor.isNegatedPowerOf2()))
return SDValue();
- unsigned Lg2 = Divisor.countTrailingZeros();
+ unsigned Lg2 = Divisor.countr_zero();
if (Lg2 == 0)
return SDValue();
@@ -15726,7 +15726,7 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
// TrailingZeroes is used to test if the mul can be lowered to
// shift+add+shift.
- unsigned TrailingZeroes = ConstValue.countTrailingZeros();
+ unsigned TrailingZeroes = ConstValue.countr_zero();
if (TrailingZeroes) {
// Conservatively do not lower to shift+add+shift if the mul might be
// folded into smul or umul.
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index fbeff1370ef3f..f30eda5bdb139 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -149,7 +149,7 @@ bool matchAArch64MulConstCombine(
// which equals to (1+2)*16-(1+2).
// TrailingZeroes is used to test if the mul can be lowered to
// shift+add+shift.
- unsigned TrailingZeroes = ConstValue.countTrailingZeros();
+ unsigned TrailingZeroes = ConstValue.countr_zero();
if (TrailingZeroes) {
// Conservatively do not lower to shift+add+shift if the mul might be
// folded into smul or umul.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index ca2d7ff2584e0..437598314ff02 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -712,11 +712,11 @@ bool AMDGPUDAGToDAGISel::isUnneededShiftMask(const SDNode *N,
assert(N->getOpcode() == ISD::AND);
const APInt &RHS = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
- if (RHS.countTrailingOnes() >= ShAmtBits)
+ if (RHS.countr_one() >= ShAmtBits)
return true;
const APInt &LHSKnownZeros = CurDAG->computeKnownBits(N->getOperand(0)).Zero;
- return (LHSKnownZeros | RHS).countTrailingOnes() >= ShAmtBits;
+ return (LHSKnownZeros | RHS).countr_one() >= ShAmtBits;
}
static bool getBaseWithOffsetUsingSplitOR(SelectionDAG &DAG, SDValue Addr,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index 2b9592d5028d6..d99a62ef716d7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -1083,7 +1083,7 @@ static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC,
// Buffer case.
const unsigned ActiveBits = DemandedElts.getActiveBits();
- const unsigned UnusedComponentsAtFront = DemandedElts.countTrailingZeros();
+ const unsigned UnusedComponentsAtFront = DemandedElts.countr_zero();
// Start assuming the prefix of elements is demanded, but possibly clear
// some other bits if there are trailing zeros (unused components at front)
@@ -1180,7 +1180,7 @@ static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC,
if (NewNumElts == 1) {
return IC.Builder.CreateInsertElement(UndefValue::get(IIVTy), NewCall,
- DemandedElts.countTrailingZeros());
+ DemandedElts.countr_zero());
}
SmallVector<int, 8> EltMask;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 4ef3c7972b736..5ea73edc9d8e8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4298,12 +4298,12 @@ bool AMDGPUInstructionSelector::isUnneededShiftMask(const MachineInstr &MI,
if (!RHS)
return false;
- if (RHS->countTrailingOnes() >= ShAmtBits)
+ if (RHS->countr_one() >= ShAmtBits)
return true;
const APInt &LHSKnownZeros =
KnownBits->getKnownZeroes(MI.getOperand(1).getReg());
- return (LHSKnownZeros | *RHS).countTrailingOnes() >= ShAmtBits;
+ return (LHSKnownZeros | *RHS).countr_one() >= ShAmtBits;
}
// Return the wave level SGPR base address if this is a wave address.
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 85dca42483941..c33250904529b 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -9699,7 +9699,7 @@ SDValue SITargetLowering::performAndCombine(SDNode *N,
(Bits == 8 || Bits == 16) && isShiftedMask_64(Mask) && !(Mask & 1)) {
if (auto *CShift = dyn_cast<ConstantSDNode>(LHS->getOperand(1))) {
unsigned Shift = CShift->getZExtValue();
- unsigned NB = CRHS->getAPIntValue().countTrailingZeros();
+ unsigned NB = CRHS->getAPIntValue().countr_zero();
unsigned Offset = NB + Shift;
if ((Offset & (Bits - 1)) == 0) { // Starts at a byte or word boundary.
SDLoc SL(N);
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 2450fa7360d2c..fbf688de637b5 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -3540,8 +3540,8 @@ void ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
static std::optional<std::pair<unsigned, unsigned>>
getContiguousRangeOfSetBits(const APInt &A) {
- unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;
- unsigned LastOne = A.countTrailingZeros();
+ unsigned FirstOne = A.getBitWidth() - A.countl_zero() - 1;
+ unsigned LastOne = A.countr_zero();
if (A.popcount() != (FirstOne - LastOne + 1))
return std::nullopt;
return std::make_pair(FirstOne, LastOne);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index c8e133e7483b6..552a24e9b649b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13838,7 +13838,7 @@ static SDValue PerformSHLSimplify(SDNode *N,
// The immediates are encoded as an 8-bit value that can be rotated.
auto LargeImm = [](const APInt &Imm) {
- unsigned Zeros = Imm.countLeadingZeros() + Imm.countTrailingZeros();
+ unsigned Zeros = Imm.countl_zero() + Imm.countr_zero();
return Imm.getBitWidth() - Zeros > 8;
};
@@ -14706,8 +14706,8 @@ static SDValue ParseBFI(SDNode *N, APInt &ToMask, APInt &FromMask) {
//
// Neither A nor B must be zero.
static bool BitsProperlyConcatenate(const APInt &A, const APInt &B) {
- unsigned LastActiveBitInA = A.countTrailingZeros();
- unsigned FirstActiveBitInB = B.getBitWidth() - B.countLeadingZeros() - 1;
+ unsigned LastActiveBitInA = A.countr_zero();
+ unsigned FirstActiveBitInB = B.getBitWidth() - B.countl_zero() - 1;
return LastActiveBitInA - 1 == FirstActiveBitInB;
}
@@ -14785,9 +14785,8 @@ static SDValue PerformBFICombine(SDNode *N, SelectionDAG &DAG) {
SDLoc dl(N);
if (NewFromMask[0] == 0)
- From1 = DAG.getNode(
- ISD::SRL, dl, VT, From1,
- DAG.getConstant(NewFromMask.countTrailingZeros(), dl, VT));
+ From1 = DAG.getNode(ISD::SRL, dl, VT, From1,
+ DAG.getConstant(NewFromMask.countr_zero(), dl, VT));
return DAG.getNode(ARMISD::BFI, dl, VT, CombineBFI.getOperand(0), From1,
DAG.getConstant(~NewToMask, dl, VT));
}
@@ -14801,7 +14800,7 @@ static SDValue PerformBFICombine(SDNode *N, SelectionDAG &DAG) {
APInt ToMask2 = ~N0.getConstantOperandAPInt(2);
if (!N0.hasOneUse() || (ToMask1 & ToMask2) != 0 ||
- ToMask1.countLeadingZeros() < ToMask2.countLeadingZeros())
+ ToMask1.countl_zero() < ToMask2.countl_zero())
return SDValue();
EVT VT = N->getValueType(0);
@@ -17736,10 +17735,10 @@ static SDValue PerformMinMaxToSatCombine(SDValue Op, SelectionDAG &DAG,
SDLoc DL(Op);
if (MinC == ~MaxC)
return DAG.getNode(ARMISD::SSAT, DL, VT, Input,
- DAG.getConstant(MinC.countTrailingOnes(), DL, VT));
+ DAG.getConstant(MinC.countr_one(), DL, VT));
if (MaxC == 0)
return DAG.getNode(ARMISD::USAT, DL, VT, Input,
- DAG.getConstant(MinC.countTrailingOnes(), DL, VT));
+ DAG.getConstant(MinC.countr_one(), DL, VT));
return SDValue();
}
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 88517ee663d1e..4d91cdf3f07e0 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -1687,9 +1687,9 @@ bool MachineConstEvaluator::evaluateCLBi(const APInt &A1, bool Zeros,
return false;
unsigned Count = 0;
if (Zeros && (Count == 0))
- Count = A1.countLeadingZeros();
+ Count = A1.countl_zero();
if (Ones && (Count == 0))
- Count = A1.countLeadingOnes();
+ Count = A1.countl_one();
Result = APInt(BW, static_cast<uint64_t>(Count), false);
return true;
}
@@ -1722,9 +1722,9 @@ bool MachineConstEvaluator::evaluateCTBi(const APInt &A1, bool Zeros,
return false;
unsigned Count = 0;
if (Zeros && (Count == 0))
- Count = A1.countTrailingZeros();
+ Count = A1.countr_zero();
if (Ones && (Count == 0))
- Count = A1.countTrailingOnes();
+ Count = A1.countr_one();
Result = APInt(BW, static_cast<uint64_t>(Count), false);
return true;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp b/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp
index d9307190ae169..3274f9162b543 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp
@@ -178,7 +178,7 @@ bool HexagonGenExtract::convert(Instruction *In) {
// CM is the shifted-left mask. Shift it back right to remove the zero
// bits on least-significant positions.
APInt M = CM->getValue().lshr(SL);
- uint32_t T = M.countTrailingOnes();
+ uint32_t T = M.countr_one();
// During the shifts some of the bits will be lost. Calculate how many
// of the original value will remain after shift right and then left.
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index d6c459f4f1cb5..5aad71a0a1c97 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -1867,7 +1867,7 @@ static unsigned getPowerOf2Factor(SDValue Val) {
continue;
const APInt &CInt = C->getAPIntValue();
if (CInt.getBoolValue())
- MaxFactor = CInt.countTrailingZeros();
+ MaxFactor = CInt.countr_zero();
}
return MaxFactor;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
index 505ec000c7d00..fe723a4ba3fbf 100644
--- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
@@ -1280,7 +1280,7 @@ bool PolynomialMultiplyRecognize::keepsHighBitsZero(Value *V,
// Assume that all inputs to the value have the high bits zero.
// Check if the value itself preserves the zeros in the high bits.
if (auto *C = dyn_cast<ConstantInt>(V))
- return C->getValue().countLeadingZeros() >= IterCount;
+ return C->getValue().countl_zero() >= IterCount;
if (auto *I = dyn_cast<Instruction>(V)) {
switch (I->getOpcode()) {
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 0dbb230214468..4bcc287d8d17a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -16033,7 +16033,7 @@ PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
SDValue N0 = N->getOperand(0);
bool IsNegPow2 = Divisor.isNegatedPowerOf2();
- unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
+ unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countr_zero();
SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e5734e13f7af8..ee163caaf53c1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9899,7 +9899,7 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
// AddC needs to have at least 32 trailing zeros.
- if (AddC->getAPIntValue().countTrailingZeros() < 32)
+ if (AddC->getAPIntValue().countr_zero() < 32)
return SDValue();
// All users should be a shift by constant less than or equal to 32. This
@@ -14138,8 +14138,8 @@ bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
return false;
// Break the MUL to two SLLI instructions and an ADD/SUB, if Imm needs
// a pair of LUI/ADDI.
- if (!Imm.isSignedIntN(12) && Imm.countTrailingZeros() < 12) {
- APInt ImmS = Imm.ashr(Imm.countTrailingZeros());
+ if (!Imm.isSignedIntN(12) && Imm.countr_zero() < 12) {
+ APInt ImmS = Imm.ashr(Imm.countr_zero());
if ((ImmS + 1).isPowerOf2() || (ImmS - 1).isPowerOf2() ||
(1 - ImmS).isPowerOf2())
return true;
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index e7aea3326e5e3..f47cc27124517 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -487,11 +487,11 @@ namespace {
assert(N->getOpcode() == ISD::AND && "Unexpected opcode");
const APInt &Val = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
- if (Val.countTrailingOnes() >= Width)
+ if (Val.countr_one() >= Width)
return true;
APInt Mask = Val | CurDAG->computeKnownBits(N->getOperand(0)).Zero;
- return Mask.countTrailingOnes() >= Width;
+ return Mask.countr_one() >= Width;
}
/// Return an SDNode that returns the value of the global base register.
@@ -4452,7 +4452,7 @@ bool X86DAGToDAGISel::shrinkAndImmediate(SDNode *And) {
// implicit zeroing of 32 bit ops. So we should check if the lower 32 bits
// are negative too.
APInt MaskVal = And1C->getAPIntValue();
- unsigned MaskLZ = MaskVal.countLeadingZeros();
+ unsigned MaskLZ = MaskVal.countl_zero();
if (!MaskLZ || (VT == MVT::i64 && MaskLZ == 32))
return false;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0ba8264c71957..377cba8eb9493 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -9413,7 +9413,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
: DAG.getConstantFP(0.0, DL, VT);
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- int FirstLoadedElt = LoadMask.countTrailingZeros();
+ int FirstLoadedElt = LoadMask.countr_zero();
SDValue EltBase = peekThroughBitcasts(Elts[FirstLoadedElt]);
EVT EltBaseVT = EltBase.getValueType();
assert(EltBaseVT.getSizeInBits() == EltBaseVT.getStoreSizeInBits() &&
@@ -11298,12 +11298,12 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
!isFoldableUseOfShuffle(BV)) {
unsigned UpperElems = NumElems / 2;
APInt UndefOrZeroMask = UndefMask | ZeroMask;
- unsigned NumUpperUndefsOrZeros = UndefOrZeroMask.countLeadingOnes();
+ unsigned NumUpperUndefsOrZeros = UndefOrZeroMask.countl_one();
if (NumUpperUndefsOrZeros >= UpperElems) {
if (VT.is512BitVector() &&
NumUpperUndefsOrZeros >= (NumElems - (NumElems / 4)))
UpperElems = NumElems - (NumElems / 4);
- bool UndefUpper = UndefMask.countLeadingOnes() >= UpperElems;
+ bool UndefUpper = UndefMask.countl_one() >= UpperElems;
MVT LowerVT = MVT::getVectorVT(EltVT, NumElems - UpperElems);
SDValue NewBV =
DAG.getBuildVector(LowerVT, dl, Op->ops().drop_back(UpperElems));
@@ -11385,7 +11385,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
// Special case for single non-zero, non-undef, element.
if (NumNonZero == 1) {
- unsigned Idx = NonZeroMask.countTrailingZeros();
+ unsigned Idx = NonZeroMask.countr_zero();
SDValue Item = Op.getOperand(Idx);
// If we have a constant or non-constant insertion into the low element of
@@ -11451,7 +11451,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
// shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
// Check if it's possible to issue this instead.
// shuffle (vload ptr)), undef, <1, 1, 1, 1>
- unsigned Idx = NonZeroMask.countTrailingZeros();
+ unsigned Idx = NonZeroMask.countr_zero();
SDValue Item = Op.getOperand(Idx);
if (Op.getNode()->isOnlyUserOf(Item.getNode()))
return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
@@ -11520,7 +11520,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
if (EVTBits == 64) {
if (NumNonZero == 1) {
// One half is zero or undef.
- unsigned Idx = NonZeroMask.countTrailingZeros();
+ unsigned Idx = NonZeroMask.countr_zero();
SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
Op.getOperand(Idx));
return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
@@ -13956,8 +13956,8 @@ static SDValue lowerShuffleAsByteShiftMask(const SDLoc &DL, MVT VT, SDValue V1,
// We need a shuffle that has zeros at one/both ends and a sequential
// shuffle from one source within.
- unsigned ZeroLo = Zeroable.countTrailingOnes();
- unsigned ZeroHi = Zeroable.countLeadingOnes();
+ unsigned ZeroLo = Zeroable.countr_one();
+ unsigned ZeroHi = Zeroable.countl_one();
if (!ZeroLo && !ZeroHi)
return SDValue();
@@ -18004,7 +18004,7 @@ static SDValue lowerShuffleAsVTRUNCAndUnpack(const SDLoc &DL, MVT VT,
return SDValue();
// Remaining elements need to be zeroable.
- if (Zeroable.countLeadingOnes() < (Mask.size() - 8))
+ if (Zeroable.countl_one() < (Mask.size() - 8))
return SDValue();
V1 = DAG.getBitcast(MVT::v4i64, V1);
@@ -19589,7 +19589,7 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
// Make sure the number of zeroable bits in the top at least covers the bits
// not covered by the subvector.
- if ((int)Zeroable.countLeadingOnes() >= (NumElts - SubvecElts)) {
+ if ((int)Zeroable.countl_one() >= (NumElts - SubvecElts)) {
assert(Src >= 0 && "Expected a source!");
MVT ExtractVT = MVT::getVectorVT(MVT::i1, SubvecElts);
SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtractVT,
@@ -24505,7 +24505,7 @@ X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
!(Subtarget.is64Bit() && VT == MVT::i64))
return SDValue();
- unsigned Lg2 = Divisor.countTrailingZeros();
+ unsigned Lg2 = Divisor.countr_zero();
// If the divisor is 2 or -2, the default expansion is better.
if (Lg2 == 1)
@@ -38117,8 +38117,7 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
EVT SrcVT = Op.getOperand(0).getValueType();
if (SrcVT.isVector()) {
unsigned NumSrcElts = SrcVT.getVectorNumElements();
- if (NumElts > NumSrcElts &&
- DemandedElts.countTrailingZeros() >= NumSrcElts)
+ if (NumElts > NumSrcElts && DemandedElts.countr_zero() >= NumSrcElts)
Known.setAllZero();
}
break;
@@ -38133,15 +38132,14 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
EVT SrcVT = Op.getOperand(1).getValueType();
if (SrcVT.isVector()) {
unsigned NumSrcElts = SrcVT.getVectorNumElements();
- if (NumElts > NumSrcElts &&
- DemandedElts.countTrailingZeros() >= NumSrcElts)
+ if (NumElts > NumSrcElts && DemandedElts.countr_zero() >= NumSrcElts)
Known.setAllZero();
}
break;
}
case X86ISD::MOVQ2DQ: {
// Move from MMX to XMM. Upper half of XMM should be 0.
- if (DemandedElts.countTrailingZeros() >= (NumElts / 2))
+ if (DemandedElts.countr_zero() >= (NumElts / 2))
Known.setAllZero();
break;
}
@@ -42932,7 +42930,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
// single shift. We can do this if the bottom bits (which are shifted
// out) are never demanded.
if (Op0.getOpcode() == X86ISD::VSRLI &&
- OriginalDemandedBits.countTrailingZeros() >= ShAmt) {
+ OriginalDemandedBits.countr_zero() >= ShAmt) {
unsigned Shift2Amt = Op0.getConstantOperandVal(1);
if (Shift2Amt < BitWidth) {
int Diff = ShAmt - Shift2Amt;
@@ -42950,8 +42948,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
// If we are only demanding sign bits then we can use the shift source directly.
unsigned NumSignBits =
TLO.DAG.ComputeNumSignBits(Op0, OriginalDemandedElts, Depth + 1);
- unsigned UpperDemandedBits =
- BitWidth - OriginalDemandedBits.countTrailingZeros();
+ unsigned UpperDemandedBits = BitWidth - OriginalDemandedBits.countr_zero();
if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= UpperDemandedBits)
return TLO.CombineTo(Op, Op0);
@@ -43012,7 +43009,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
// If any of the demanded bits are produced by the sign extension, we also
// demand the input sign bit.
- if (OriginalDemandedBits.countLeadingZeros() < ShAmt)
+ if (OriginalDemandedBits.countl_zero() < ShAmt)
DemandedMask.setSignBit();
if (SimplifyDemandedBits(Op0, DemandedMask, OriginalDemandedElts, Known,
@@ -43026,7 +43023,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
if (Known.Zero[BitWidth - ShAmt - 1] ||
- OriginalDemandedBits.countLeadingZeros() >= ShAmt)
+ OriginalDemandedBits.countl_zero() >= ShAmt)
return TLO.CombineTo(
Op, TLO.DAG.getNode(X86ISD::VSRLI, SDLoc(Op), VT, Op0, Op1));
@@ -43168,7 +43165,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
// Don't attempt this on AVX512 as it might affect broadcast folding.
// TODO: Should we attempt this for i32/i16 splats? They tend to be slower.
if ((BitWidth == 64) && SrcVT.isScalarInteger() && !Subtarget.hasAVX512() &&
- OriginalDemandedBits.countLeadingZeros() >= (BitWidth / 2) &&
+ OriginalDemandedBits.countl_zero() >= (BitWidth / 2) &&
Src->hasOneUse()) {
MVT NewSrcVT = MVT::getIntegerVT(BitWidth / 2);
SDValue NewSrc =
@@ -43194,7 +43191,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
unsigned NumElts = SrcVT.getVectorNumElements();
// If we don't need the sign bits at all just return zero.
- if (OriginalDemandedBits.countTrailingZeros() >= NumElts)
+ if (OriginalDemandedBits.countr_zero() >= NumElts)
return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
// See if we only demand bits from the lower 128-bit vector.
@@ -43286,7 +43283,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
- unsigned DemandedBitsLZ = OriginalDemandedBits.countLeadingZeros();
+ unsigned DemandedBitsLZ = OriginalDemandedBits.countl_zero();
APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ);
// If the demanded bits has leading zeroes, we don't demand those from the
@@ -43342,7 +43339,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
unsigned ShAmt = Op.getConstantOperandVal(1);
unsigned BitWidth = DemandedBits.getBitWidth();
unsigned NumSignBits = DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
- unsigned UpperDemandedBits = BitWidth - DemandedBits.countTrailingZeros();
+ unsigned UpperDemandedBits = BitWidth - DemandedBits.countr_zero();
if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= UpperDemandedBits)
return Op0;
break;
@@ -43415,7 +43412,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
"Multiple identity shuffles detected");
if (IdentityOp != 0)
- return DAG.getBitcast(VT, ShuffleOps[IdentityOp.countTrailingZeros()]);
+ return DAG.getBitcast(VT, ShuffleOps[IdentityOp.countr_zero()]);
}
}
@@ -44054,7 +44051,7 @@ static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG,
if (getTargetConstantBitsFromNode(N0, 64, UndefElts, EltBits)) {
SDLoc DL(N0);
// Handle zero-extension of i32 with MOVD.
- if (EltBits[0].countLeadingZeros() >= 32)
+ if (EltBits[0].countl_zero() >= 32)
return DAG.getNode(X86ISD::MMX_MOVW2D, DL, VT,
DAG.getConstant(EltBits[0].trunc(32), DL, MVT::i32));
// Else, bitcast to a double.
@@ -48059,7 +48056,7 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
// If this can be matched by a zero extend, don't optimize.
if (MaskVal.isMask()) {
- unsigned TO = MaskVal.countTrailingOnes();
+ unsigned TO = MaskVal.countr_one();
if (TO >= 8 && isPowerOf2_32(TO))
return SDValue();
}
@@ -49095,7 +49092,7 @@ static SDValue combineAndMaskToShift(SDNode *N, SelectionDAG &DAG,
return SDValue();
SDLoc DL(N);
- unsigned ShiftVal = SplatVal.countTrailingOnes();
+ unsigned ShiftVal = SplatVal.countr_one();
SDValue ShAmt = DAG.getTargetConstant(EltBitWidth - ShiftVal, DL, MVT::i8);
SDValue Shift = DAG.getNode(X86ISD::VSRLI, DL, VT, Op0, ShAmt);
return DAG.getBitcast(N->getValueType(0), Shift);
@@ -50834,7 +50831,7 @@ static int getOneTrueElt(SDValue V) {
auto *ConstNode = dyn_cast<ConstantSDNode>(Op);
if (!ConstNode)
return -1;
- if (ConstNode->getAPIntValue().countTrailingOnes() >= 1) {
+ if (ConstNode->getAPIntValue().countr_one() >= 1) {
// If we already found a one, this is too many.
if (TrueIndex >= 0)
return -1;
@@ -54210,7 +54207,7 @@ static SDValue combineMOVMSK(SDNode *N, SelectionDAG &DAG,
ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
LHS = DAG.getBitcast(ShiftVT, LHS);
}
- unsigned ShiftAmt = KnownRHS.getConstant().countLeadingZeros();
+ unsigned ShiftAmt = KnownRHS.getConstant().countl_zero();
LHS = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, ShiftVT, LHS,
ShiftAmt, DAG);
LHS = DAG.getNOT(DL, DAG.getBitcast(SrcVT, LHS), SrcVT);
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index 8fddd0037999d..575cf4d3dced3 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -1680,12 +1680,12 @@ def : Pat<(and GR64:$src, 0xff),
def BTRXForm : SDNodeXForm<imm, [{
// Transformation function: Find the lowest 0.
- return getI64Imm((uint8_t)N->getAPIntValue().countTrailingOnes(), SDLoc(N));
+ return getI64Imm((uint8_t)N->getAPIntValue().countr_one(), SDLoc(N));
}]>;
def BTCBTSXForm : SDNodeXForm<imm, [{
// Transformation function: Find the lowest 1.
- return getI64Imm((uint8_t)N->getAPIntValue().countTrailingZeros(), SDLoc(N));
+ return getI64Imm((uint8_t)N->getAPIntValue().countr_zero(), SDLoc(N));
}]>;
def BTRMask64 : ImmLeaf<i64, [{
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index 17a94ca896f23..eddb74cabef66 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -797,7 +797,7 @@ static Value *checkForNegativeOperand(BinaryOperator &I,
// LHS = XOR(Y, C1), Y = AND(Z, C2), C1 == (C2 + 1) => LHS == NEG(OR(Z, ~C2))
// ADD(LHS, RHS) == SUB(RHS, OR(Z, ~C2))
if (match(LHS, m_Xor(m_Value(Y), m_APInt(C1))))
- if (C1->countTrailingZeros() == 0)
+ if (C1->countr_zero() == 0)
if (match(Y, m_And(m_Value(Z), m_APInt(C2))) && *C1 == (*C2 + 1)) {
Value *NewOr = Builder.CreateOr(Z, ~(*C2));
return Builder.CreateSub(RHS, NewOr, "sub");
@@ -1449,7 +1449,7 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
// (A & 2^C1) + A => A & (2^C1 - 1) iff bit C1 in A is a sign bit
if (match(&I, m_c_Add(m_And(m_Value(A), m_APInt(C1)), m_Deferred(A))) &&
- C1->isPowerOf2() && (ComputeNumSignBits(A) > C1->countLeadingZeros())) {
+ C1->isPowerOf2() && (ComputeNumSignBits(A) > C1->countl_zero())) {
Constant *NewMask = ConstantInt::get(RHS->getType(), *C1 - 1);
return BinaryOperator::CreateAnd(A, NewMask);
}
@@ -1525,7 +1525,7 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
const APInt *NegPow2C;
if (match(&I, m_c_Add(m_OneUse(m_Mul(m_Value(A), m_NegatedPower2(NegPow2C))),
m_Value(B)))) {
- Constant *ShiftAmtC = ConstantInt::get(Ty, NegPow2C->countTrailingZeros());
+ Constant *ShiftAmtC = ConstantInt::get(Ty, NegPow2C->countr_zero());
Value *Shl = Builder.CreateShl(A, ShiftAmtC);
return BinaryOperator::CreateSub(B, Shl);
}
@@ -2335,7 +2335,7 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
const APInt *AddC, *AndC;
if (match(Op0, m_Add(m_Value(X), m_APInt(AddC))) &&
match(Op1, m_And(m_Specific(X), m_APInt(AndC)))) {
- unsigned Cttz = AddC->countTrailingZeros();
+ unsigned Cttz = AddC->countr_zero();
APInt HighMask(APInt::getHighBitsSet(BitWidth, BitWidth - Cttz));
if ((HighMask & *AndC).isZero())
return BinaryOperator::CreateAnd(Op0, ConstantInt::get(Ty, ~(*AndC)));
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index e389f3d6bd092..760dd726b50c6 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2113,16 +2113,16 @@ static Instruction *canonicalizeLogicFirst(BinaryOperator &I,
return nullptr;
unsigned Width = Ty->getScalarSizeInBits();
- unsigned LastOneMath = Width - C2->countTrailingZeros();
+ unsigned LastOneMath = Width - C2->countr_zero();
switch (OpC) {
case Instruction::And:
- if (C->countLeadingOnes() < LastOneMath)
+ if (C->countl_one() < LastOneMath)
return nullptr;
break;
case Instruction::Xor:
case Instruction::Or:
- if (C->countLeadingZeros() < LastOneMath)
+ if (C->countl_zero() < LastOneMath)
return nullptr;
break;
default:
@@ -2240,7 +2240,7 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
if (match(Op0, m_Add(m_Value(X), m_APInt(AddC)))) {
// If we add zeros to every bit below a mask, the add has no effect:
// (X + AddC) & LowMaskC --> X & LowMaskC
- unsigned Ctlz = C->countLeadingZeros();
+ unsigned Ctlz = C->countl_zero();
APInt LowMask(APInt::getLowBitsSet(Width, Width - Ctlz));
if ((*AddC & LowMask).isZero())
return BinaryOperator::CreateAnd(X, Op1);
@@ -2357,7 +2357,7 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
const APInt *C3 = C;
Value *X;
if (C3->isPowerOf2()) {
- Constant *Log2C3 = ConstantInt::get(Ty, C3->countTrailingZeros());
+ Constant *Log2C3 = ConstantInt::get(Ty, C3->countr_zero());
if (match(Op0, m_OneUse(m_LShr(m_Shl(m_ImmConstant(C1), m_Value(X)),
m_ImmConstant(C2)))) &&
match(C1, m_Power2())) {
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
index 118f7174f1156..71fe7fd558b0d 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -1419,7 +1419,7 @@ Instruction *InstCombinerImpl::transformSExtICmp(ICmpInst *Cmp,
if (!Op1C->isZero() == (Pred == ICmpInst::ICMP_NE)) {
// sext ((x & 2^n) == 0) -> (x >> n) - 1
// sext ((x & 2^n) != 2^n) -> (x >> n) - 1
- unsigned ShiftAmt = KnownZeroMask.countTrailingZeros();
+ unsigned ShiftAmt = KnownZeroMask.countr_zero();
// Perform a right shift to place the desired bit in the LSB.
if (ShiftAmt)
In = Builder.CreateLShr(In,
@@ -1433,7 +1433,7 @@ Instruction *InstCombinerImpl::transformSExtICmp(ICmpInst *Cmp,
} else {
// sext ((x & 2^n) != 0) -> (x << bitwidth-n) a>> bitwidth-1
// sext ((x & 2^n) == 2^n) -> (x << bitwidth-n) a>> bitwidth-1
- unsigned ShiftAmt = KnownZeroMask.countLeadingZeros();
+ unsigned ShiftAmt = KnownZeroMask.countl_zero();
// Perform a left shift to place the desired bit in the MSB.
if (ShiftAmt)
In = Builder.CreateShl(In,
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 20622da742b2b..a1f65bd1efd42 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -1058,9 +1058,9 @@ Instruction *InstCombinerImpl::foldICmpShrConstConst(ICmpInst &I, Value *A,
int Shift;
if (IsAShr && AP1.isNegative())
- Shift = AP1.countLeadingOnes() - AP2.countLeadingOnes();
+ Shift = AP1.countl_one() - AP2.countl_one();
else
- Shift = AP1.countLeadingZeros() - AP2.countLeadingZeros();
+ Shift = AP1.countl_zero() - AP2.countl_zero();
if (Shift > 0) {
if (IsAShr && AP1 == AP2.ashr(Shift)) {
@@ -1097,7 +1097,7 @@ Instruction *InstCombinerImpl::foldICmpShlConstConst(ICmpInst &I, Value *A,
if (AP2.isZero())
return nullptr;
- unsigned AP2TrailingZeros = AP2.countTrailingZeros();
+ unsigned AP2TrailingZeros = AP2.countr_zero();
if (!AP1 && AP2TrailingZeros != 0)
return getICmp(
@@ -1108,7 +1108,7 @@ Instruction *InstCombinerImpl::foldICmpShlConstConst(ICmpInst &I, Value *A,
return getICmp(I.ICMP_EQ, A, ConstantInt::getNullValue(A->getType()));
// Get the distance between the lowest bits that are set.
- int Shift = AP1.countTrailingZeros() - AP2TrailingZeros;
+ int Shift = AP1.countr_zero() - AP2TrailingZeros;
if (Shift > 0 && AP2.shl(Shift) == AP1)
return getICmp(I.ICMP_EQ, A, ConstantInt::get(A->getType(), Shift));
@@ -1143,7 +1143,7 @@ static Instruction *processUGT_ADDCST_ADD(ICmpInst &I, Value *A, Value *B,
// If CI2 is 2^7, 2^15, 2^31, then it might be an sadd.with.overflow.
if (!CI2->getValue().isPowerOf2())
return nullptr;
- unsigned NewWidth = CI2->getValue().countTrailingZeros();
+ unsigned NewWidth = CI2->getValue().countr_zero();
if (NewWidth != 7 && NewWidth != 15 && NewWidth != 31)
return nullptr;
@@ -1517,7 +1517,7 @@ Instruction *InstCombinerImpl::foldICmpTruncConstant(ICmpInst &Cmp,
KnownBits Known = computeKnownBits(X, 0, &Cmp);
// If all the high bits are known, we can do this xform.
- if ((Known.Zero | Known.One).countLeadingOnes() >= SrcBits - DstBits) {
+ if ((Known.Zero | Known.One).countl_one() >= SrcBits - DstBits) {
// Pull in the high bits from known-ones set.
APInt NewRHS = C.zext(SrcBits);
NewRHS |= Known.One & APInt::getHighBitsSet(SrcBits, SrcBits - DstBits);
@@ -2268,7 +2268,7 @@ Instruction *InstCombinerImpl::foldICmpShlConstant(ICmpInst &Cmp,
// free on the target. It has the additional benefit of comparing to a
// smaller constant that may be more target-friendly.
unsigned Amt = ShiftAmt->getLimitedValue(TypeBits - 1);
- if (Shl->hasOneUse() && Amt != 0 && C.countTrailingZeros() >= Amt &&
+ if (Shl->hasOneUse() && Amt != 0 && C.countr_zero() >= Amt &&
DL.isLegalInteger(TypeBits - Amt)) {
Type *TruncTy = IntegerType::get(Cmp.getContext(), TypeBits - Amt);
if (auto *ShVTy = dyn_cast<VectorType>(ShType))
@@ -2316,9 +2316,8 @@ Instruction *InstCombinerImpl::foldICmpShrConstant(ICmpInst &Cmp,
assert(ShiftValC->uge(C) && "Expected simplify of compare");
assert((IsUGT || !C.isZero()) && "Expected X u< 0 to simplify");
- unsigned CmpLZ =
- IsUGT ? C.countLeadingZeros() : (C - 1).countLeadingZeros();
- unsigned ShiftLZ = ShiftValC->countLeadingZeros();
+ unsigned CmpLZ = IsUGT ? C.countl_zero() : (C - 1).countl_zero();
+ unsigned ShiftLZ = ShiftValC->countl_zero();
Constant *NewC = ConstantInt::get(Shr->getType(), CmpLZ - ShiftLZ);
auto NewPred = IsUGT ? CmpInst::ICMP_ULT : CmpInst::ICMP_UGE;
return new ICmpInst(NewPred, Shr->getOperand(1), NewC);
@@ -4505,7 +4504,7 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
!C->isOne()) {
// icmp eq/ne (X * C), (Y * C) --> icmp (X & Mask), (Y & Mask)
// Mask = -1 >> count-trailing-zeros(C).
- if (unsigned TZs = C->countTrailingZeros()) {
+ if (unsigned TZs = C->countr_zero()) {
Constant *Mask = ConstantInt::get(
BO0->getType(),
APInt::getLowBitsSet(C->getBitWidth(), C->getBitWidth() - TZs));
@@ -4759,7 +4758,7 @@ Instruction *InstCombinerImpl::foldICmpEquality(ICmpInst &I) {
// (B & (Pow2C-1)) != zext A --> A != trunc B
const APInt *MaskC;
if (match(Op0, m_And(m_Value(B), m_LowBitMask(MaskC))) &&
- MaskC->countTrailingOnes() == A->getType()->getScalarSizeInBits())
+ MaskC->countr_one() == A->getType()->getScalarSizeInBits())
return new ICmpInst(Pred, A, Builder.CreateTrunc(B, A->getType()));
}
@@ -5285,7 +5284,7 @@ static Instruction *processUMulZExtIdiom(ICmpInst &I, Value *MulVal,
return nullptr;
if (ConstantInt *CI = dyn_cast<ConstantInt>(BO->getOperand(1))) {
const APInt &CVal = CI->getValue();
- if (CVal.getBitWidth() - CVal.countLeadingZeros() > MulWidth)
+ if (CVal.getBitWidth() - CVal.countl_zero() > MulWidth)
return nullptr;
} else {
// In this case we could have the operand of the binary operation
@@ -5466,12 +5465,12 @@ static APInt getDemandedBitsLHSMask(ICmpInst &I, unsigned BitWidth) {
// bits doesn't impact the outcome of the comparison, because any value
// greater than the RHS must
diff er in a bit higher than these due to carry.
case ICmpInst::ICMP_UGT:
- return APInt::getBitsSetFrom(BitWidth, RHS->countTrailingOnes());
+ return APInt::getBitsSetFrom(BitWidth, RHS->countr_one());
// Similarly, for a ULT comparison, we don't care about the trailing zeros.
// Any value less than the RHS must
diff er in a higher bit because of carries.
case ICmpInst::ICMP_ULT:
- return APInt::getBitsSetFrom(BitWidth, RHS->countTrailingZeros());
+ return APInt::getBitsSetFrom(BitWidth, RHS->countr_zero());
default:
return APInt::getAllOnes(BitWidth);
@@ -5770,14 +5769,14 @@ Instruction *InstCombinerImpl::foldICmpUsingKnownBits(ICmpInst &I) {
const APInt *C1;
if (match(LHS, m_Shl(m_Power2(C1), m_Value(X)))) {
Type *XTy = X->getType();
- unsigned Log2C1 = C1->countTrailingZeros();
+ unsigned Log2C1 = C1->countr_zero();
APInt C2 = Op0KnownZeroInverted;
APInt C2Pow2 = (C2 & ~(*C1 - 1)) + *C1;
if (C2Pow2.isPowerOf2()) {
// iff (C1 is pow2) & ((C2 & ~(C1-1)) + C1) is pow2):
// ((C1 << X) & C2) == 0 -> X >= (Log2(C2+C1) - Log2(C1))
// ((C1 << X) & C2) != 0 -> X < (Log2(C2+C1) - Log2(C1))
- unsigned Log2C2 = C2Pow2.countTrailingZeros();
+ unsigned Log2C2 = C2Pow2.countr_zero();
auto *CmpC = ConstantInt::get(XTy, Log2C2 - Log2C1);
auto NewPred =
Pred == CmpInst::ICMP_EQ ? CmpInst::ICMP_UGE : CmpInst::ICMP_ULT;
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index 97f129e200de7..c95bde43be093 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -270,7 +270,7 @@ Instruction *InstCombinerImpl::visitMul(BinaryOperator &I) {
if (match(Op0, m_ZExtOrSExt(m_Value(X))) &&
match(Op1, m_APIntAllowUndef(NegPow2C))) {
unsigned SrcWidth = X->getType()->getScalarSizeInBits();
- unsigned ShiftAmt = NegPow2C->countTrailingZeros();
+ unsigned ShiftAmt = NegPow2C->countr_zero();
if (ShiftAmt >= BitWidth - SrcWidth) {
Value *N = Builder.CreateNeg(X, X->getName() + ".neg");
Value *Z = Builder.CreateZExt(N, Ty, N->getName() + ".z");
@@ -1402,7 +1402,7 @@ Instruction *InstCombinerImpl::visitSDiv(BinaryOperator &I) {
KnownBits KnownDividend = computeKnownBits(Op0, 0, &I);
if (!I.isExact() &&
(match(Op1, m_Power2(Op1C)) || match(Op1, m_NegatedPower2(Op1C))) &&
- KnownDividend.countMinTrailingZeros() >= Op1C->countTrailingZeros()) {
+ KnownDividend.countMinTrailingZeros() >= Op1C->countr_zero()) {
I.setIsExact();
return &I;
}
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index f8d4e05e9eb8d..0f8a327177ec6 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -587,8 +587,7 @@ static bool canEvaluateShifted(Value *V, unsigned NumBits, bool IsLeftShift,
const APInt *MulConst;
// We can fold (shr (mul X, -(1 << C)), C) -> (and (neg X), C`)
return !IsLeftShift && match(I->getOperand(1), m_APInt(MulConst)) &&
- MulConst->isNegatedPowerOf2() &&
- MulConst->countTrailingZeros() == NumBits;
+ MulConst->isNegatedPowerOf2() && MulConst->countr_zero() == NumBits;
}
}
}
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index ee75279ec7218..b8841274a701c 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -168,7 +168,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// If the high-bits of an ADD/SUB/MUL are not demanded, then we do not care
// about the high bits of the operands.
auto simplifyOperandsBasedOnUnusedHighBits = [&](APInt &DemandedFromOps) {
- unsigned NLZ = DemandedMask.countLeadingZeros();
+ unsigned NLZ = DemandedMask.countl_zero();
// Right fill the mask of bits for the operands to demand the most
// significant bit and all those below it.
DemandedFromOps = APInt::getLowBitsSet(BitWidth, BitWidth - NLZ);
@@ -393,7 +393,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// The shift amount must be valid (not poison) in the narrow type, and
// it must not be greater than the high bits demanded of the result.
if (C->ult(VTy->getScalarSizeInBits()) &&
- C->ule(DemandedMask.countLeadingZeros())) {
+ C->ule(DemandedMask.countl_zero())) {
// trunc (lshr X, C) --> lshr (trunc X), C
IRBuilderBase::InsertPointGuard Guard(Builder);
Builder.SetInsertPoint(I);
@@ -508,7 +508,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// Right fill the mask of bits for the operands to demand the most
// significant bit and all those below it.
- unsigned NLZ = DemandedMask.countLeadingZeros();
+ unsigned NLZ = DemandedMask.countl_zero();
APInt DemandedFromOps = APInt::getLowBitsSet(BitWidth, BitWidth - NLZ);
if (ShrinkDemandedConstant(I, 1, DemandedFromOps) ||
SimplifyDemandedBits(I, 1, DemandedFromOps, RHSKnown, Depth + 1))
@@ -517,7 +517,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// If low order bits are not demanded and known to be zero in one operand,
// then we don't need to demand them from the other operand, since they
// can't cause overflow into any bits that are demanded in the result.
- unsigned NTZ = (~DemandedMask & RHSKnown.Zero).countTrailingOnes();
+ unsigned NTZ = (~DemandedMask & RHSKnown.Zero).countr_one();
APInt DemandedFromLHS = DemandedFromOps;
DemandedFromLHS.clearLowBits(NTZ);
if (ShrinkDemandedConstant(I, 0, DemandedFromLHS) ||
@@ -539,7 +539,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
case Instruction::Sub: {
// Right fill the mask of bits for the operands to demand the most
// significant bit and all those below it.
- unsigned NLZ = DemandedMask.countLeadingZeros();
+ unsigned NLZ = DemandedMask.countl_zero();
APInt DemandedFromOps = APInt::getLowBitsSet(BitWidth, BitWidth - NLZ);
if (ShrinkDemandedConstant(I, 1, DemandedFromOps) ||
SimplifyDemandedBits(I, 1, DemandedFromOps, RHSKnown, Depth + 1))
@@ -548,7 +548,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// If low order bits are not demanded and are known to be zero in RHS,
// then we don't need to demand them from LHS, since they can't cause a
// borrow from any bits that are demanded in the result.
- unsigned NTZ = (~DemandedMask & RHSKnown.Zero).countTrailingOnes();
+ unsigned NTZ = (~DemandedMask & RHSKnown.Zero).countr_one();
APInt DemandedFromLHS = DemandedFromOps;
DemandedFromLHS.clearLowBits(NTZ);
if (ShrinkDemandedConstant(I, 0, DemandedFromLHS) ||
@@ -578,10 +578,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// The LSB of X*Y is set only if (X & 1) == 1 and (Y & 1) == 1.
// If we demand exactly one bit N and we have "X * (C' << N)" where C' is
// odd (has LSB set), then the left-shifted low bit of X is the answer.
- unsigned CTZ = DemandedMask.countTrailingZeros();
+ unsigned CTZ = DemandedMask.countr_zero();
const APInt *C;
- if (match(I->getOperand(1), m_APInt(C)) &&
- C->countTrailingZeros() == CTZ) {
+ if (match(I->getOperand(1), m_APInt(C)) && C->countr_zero() == CTZ) {
Constant *ShiftC = ConstantInt::get(VTy, CTZ);
Instruction *Shl = BinaryOperator::CreateShl(I->getOperand(0), ShiftC);
return InsertNewInstWith(Shl, *I);
@@ -619,7 +618,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
Value *X;
Constant *C;
- if (DemandedMask.countTrailingZeros() >= ShiftAmt &&
+ if (DemandedMask.countr_zero() >= ShiftAmt &&
match(I->getOperand(0), m_LShr(m_ImmConstant(C), m_Value(X)))) {
Constant *LeftShiftAmtC = ConstantInt::get(VTy, ShiftAmt);
Constant *NewC = ConstantExpr::getShl(C, LeftShiftAmtC);
@@ -664,7 +663,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// This is a variable shift, so we can't shift the demand mask by a known
// amount. But if we are not demanding high bits, then we are not
// demanding those bits from the pre-shifted operand either.
- if (unsigned CTLZ = DemandedMask.countLeadingZeros()) {
+ if (unsigned CTLZ = DemandedMask.countl_zero()) {
APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ));
if (SimplifyDemandedBits(I, 0, DemandedFromOp, Known, Depth + 1)) {
// We can't guarantee that nsw/nuw hold after simplifying the operand.
@@ -683,11 +682,10 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// If we are just demanding the shifted sign bit and below, then this can
// be treated as an ASHR in disguise.
- if (DemandedMask.countLeadingZeros() >= ShiftAmt) {
+ if (DemandedMask.countl_zero() >= ShiftAmt) {
// If we only want bits that already match the signbit then we don't
// need to shift.
- unsigned NumHiDemandedBits =
- BitWidth - DemandedMask.countTrailingZeros();
+ unsigned NumHiDemandedBits = BitWidth - DemandedMask.countr_zero();
unsigned SignBits =
ComputeNumSignBits(I->getOperand(0), Depth + 1, CxtI);
if (SignBits >= NumHiDemandedBits)
@@ -734,7 +732,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// If we only want bits that already match the signbit then we don't need
// to shift.
- unsigned NumHiDemandedBits = BitWidth - DemandedMask.countTrailingZeros();
+ unsigned NumHiDemandedBits = BitWidth - DemandedMask.countr_zero();
if (SignBits >= NumHiDemandedBits)
return I->getOperand(0);
@@ -757,7 +755,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
// If any of the high bits are demanded, we should set the sign bit as
// demanded.
- if (DemandedMask.countLeadingZeros() <= ShiftAmt)
+ if (DemandedMask.countl_zero() <= ShiftAmt)
DemandedMaskIn.setSignBit();
// If the shift is exact, then it does demand the low bits (and knows that
@@ -797,7 +795,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
const APInt *SA;
if (match(I->getOperand(1), m_APInt(SA))) {
// TODO: Take the demanded mask of the result into account.
- unsigned RHSTrailingZeros = SA->countTrailingZeros();
+ unsigned RHSTrailingZeros = SA->countr_zero();
APInt DemandedMaskIn =
APInt::getHighBitsSet(BitWidth, BitWidth - RHSTrailingZeros);
if (SimplifyDemandedBits(I, 0, DemandedMaskIn, LHSKnown, Depth + 1)) {
@@ -808,8 +806,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
}
// Increase high zero bits from the input.
- Known.Zero.setHighBits(std::min(
- BitWidth, LHSKnown.Zero.countLeadingOnes() + RHSTrailingZeros));
+ Known.Zero.setHighBits(
+ std::min(BitWidth, LHSKnown.Zero.countl_one() + RHSTrailingZeros));
} else {
computeKnownBits(I, Known, Depth, CxtI);
}
@@ -897,8 +895,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
case Intrinsic::bswap: {
// If the only bits demanded come from one byte of the bswap result,
// just shift the input byte into position to eliminate the bswap.
- unsigned NLZ = DemandedMask.countLeadingZeros();
- unsigned NTZ = DemandedMask.countTrailingZeros();
+ unsigned NLZ = DemandedMask.countl_zero();
+ unsigned NTZ = DemandedMask.countr_zero();
// Round NTZ down to the next byte. If we have 11 trailing zeros, then
// we need all the bits down to bit 8. Likewise, round NLZ. If we
@@ -951,7 +949,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// The lowest non-zero bit of DemandMask is higher than the highest
// non-zero bit of C.
const APInt *C;
- unsigned CTZ = DemandedMask.countTrailingZeros();
+ unsigned CTZ = DemandedMask.countr_zero();
if (match(II->getArgOperand(1), m_APInt(C)) &&
CTZ >= C->getActiveBits())
return II->getArgOperand(0);
@@ -963,9 +961,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// non-one bit of C.
// This comes from using DeMorgans on the above umax example.
const APInt *C;
- unsigned CTZ = DemandedMask.countTrailingZeros();
+ unsigned CTZ = DemandedMask.countr_zero();
if (match(II->getArgOperand(1), m_APInt(C)) &&
- CTZ >= C->getBitWidth() - C->countLeadingOnes())
+ CTZ >= C->getBitWidth() - C->countl_one())
return II->getArgOperand(0);
break;
}
@@ -1071,7 +1069,7 @@ Value *InstCombinerImpl::SimplifyMultipleUseDemandedBits(
break;
}
case Instruction::Add: {
- unsigned NLZ = DemandedMask.countLeadingZeros();
+ unsigned NLZ = DemandedMask.countl_zero();
APInt DemandedFromOps = APInt::getLowBitsSet(BitWidth, BitWidth - NLZ);
// If an operand adds zeros to every bit below the highest demanded bit,
@@ -1087,7 +1085,7 @@ Value *InstCombinerImpl::SimplifyMultipleUseDemandedBits(
break;
}
case Instruction::Sub: {
- unsigned NLZ = DemandedMask.countLeadingZeros();
+ unsigned NLZ = DemandedMask.countl_zero();
APInt DemandedFromOps = APInt::getLowBitsSet(BitWidth, BitWidth - NLZ);
// If an operand subtracts zeros from every bit below the highest demanded
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index 4f8ea32f171cc..d09a246089634 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -3237,10 +3237,10 @@ Instruction *InstCombinerImpl::visitSwitchInst(SwitchInst &SI) {
// Compute the number of leading bits we can ignore.
// TODO: A better way to determine this would use ComputeNumSignBits().
for (const auto &C : SI.cases()) {
- LeadingKnownZeros = std::min(
- LeadingKnownZeros, C.getCaseValue()->getValue().countLeadingZeros());
- LeadingKnownOnes = std::min(
- LeadingKnownOnes, C.getCaseValue()->getValue().countLeadingOnes());
+ LeadingKnownZeros =
+ std::min(LeadingKnownZeros, C.getCaseValue()->getValue().countl_zero());
+ LeadingKnownOnes =
+ std::min(LeadingKnownOnes, C.getCaseValue()->getValue().countl_one());
}
unsigned NewWidth = Known.getBitWidth() - std::max(LeadingKnownZeros, LeadingKnownOnes);
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 9ec0f1558d522..9107c6309666c 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -2487,7 +2487,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
if (ConstantInt *Elt =
dyn_cast<ConstantInt>(ConstArg->getAggregateElement(Idx))) {
const APInt &V = Elt->getValue();
- APInt V2 = APInt(V.getBitWidth(), 1) << V.countTrailingZeros();
+ APInt V2 = APInt(V.getBitWidth(), 1) << V.countr_zero();
Elements.push_back(ConstantInt::get(EltTy, V2));
} else {
Elements.push_back(ConstantInt::get(EltTy, 1));
@@ -2497,7 +2497,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
} else {
if (ConstantInt *Elt = dyn_cast<ConstantInt>(ConstArg)) {
const APInt &V = Elt->getValue();
- APInt V2 = APInt(V.getBitWidth(), 1) << V.countTrailingZeros();
+ APInt V2 = APInt(V.getBitWidth(), 1) << V.countr_zero();
ShadowMul = ConstantInt::get(Ty, V2);
} else {
ShadowMul = ConstantInt::get(Ty, 1);
diff --git a/llvm/lib/Transforms/Scalar/BDCE.cpp b/llvm/lib/Transforms/Scalar/BDCE.cpp
index 187927b3dede4..24d2f3d97f5ec 100644
--- a/llvm/lib/Transforms/Scalar/BDCE.cpp
+++ b/llvm/lib/Transforms/Scalar/BDCE.cpp
@@ -116,7 +116,7 @@ static bool bitTrackingDCE(Function &F, DemandedBits &DB) {
const uint32_t SrcBitSize = SE->getSrcTy()->getScalarSizeInBits();
auto *const DstTy = SE->getDestTy();
const uint32_t DestBitSize = DstTy->getScalarSizeInBits();
- if (Demanded.countLeadingZeros() >= (DestBitSize - SrcBitSize)) {
+ if (Demanded.countl_zero() >= (DestBitSize - SrcBitSize)) {
clearAssumptionsOfUsers(SE, DB);
IRBuilder<> Builder(SE);
I.replaceAllUsesWith(
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index f3d263cbde2e8..c2b64c0e41a42 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -4379,7 +4379,7 @@ void LSRInstance::GenerateCrossUseConstantOffsets() {
if ((C->getAPInt() + NewF.BaseOffset)
.abs()
.slt(std::abs(NewF.BaseOffset)) &&
- (C->getAPInt() + NewF.BaseOffset).countTrailingZeros() >=
+ (C->getAPInt() + NewF.BaseOffset).countr_zero() >=
(unsigned)llvm::countr_zero<uint64_t>(NewF.BaseOffset))
goto skip_formula;
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 0b427e167bb26..53de2e0158968 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11170,8 +11170,8 @@ void BoUpSLP::computeMinimumValueSizes() {
// we can truncate the roots to this narrower type.
for (auto *Root : TreeRoot) {
auto Mask = DB->getDemandedBits(cast<Instruction>(Root));
- MaxBitWidth = std::max<unsigned>(
- Mask.getBitWidth() - Mask.countLeadingZeros(), MaxBitWidth);
+ MaxBitWidth = std::max<unsigned>(Mask.getBitWidth() - Mask.countl_zero(),
+ MaxBitWidth);
}
// True if the roots can be zero-extended back to their original type, rather
diff --git a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
index 79f2f0643d11d..ae3ef04d844c0 100644
--- a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
@@ -1983,8 +1983,8 @@ TEST_F(AMDGPUGISelMITest, TestKnownBitsAssertAlign) {
auto CheckBits = [&](unsigned NumBits, unsigned Idx) {
Res = GetKB(Idx);
EXPECT_EQ(64u, Res.getBitWidth());
- EXPECT_EQ(NumBits - 1, Res.Zero.countTrailingOnes());
- EXPECT_EQ(64u, Res.One.countTrailingZeros());
+ EXPECT_EQ(NumBits - 1, Res.Zero.countr_one());
+ EXPECT_EQ(64u, Res.One.countr_zero());
EXPECT_EQ(Align(1ull << (NumBits - 1)), Info.computeKnownAlignment(Copies[Idx]));
};
@@ -2014,5 +2014,5 @@ TEST_F(AArch64GISelMITest, TestKnownBitsUADDO) {
GISelKnownBits Info(*MF);
KnownBits Res = Info.getKnownBits(CopyOverflow);
EXPECT_EQ(0u, Res.One.getZExtValue());
- EXPECT_EQ(31u, Res.Zero.countLeadingOnes());
+ EXPECT_EQ(31u, Res.Zero.countl_one());
}
diff --git a/llvm/unittests/IR/ConstantRangeTest.cpp b/llvm/unittests/IR/ConstantRangeTest.cpp
index 5d1931ebf6025..cb7d01759bee7 100644
--- a/llvm/unittests/IR/ConstantRangeTest.cpp
+++ b/llvm/unittests/IR/ConstantRangeTest.cpp
@@ -2398,17 +2398,16 @@ TEST_F(ConstantRangeTest, Abs) {
}
TEST_F(ConstantRangeTest, Ctlz) {
- TestUnaryOpExhaustive([](const ConstantRange &CR) { return CR.ctlz(); },
- [](const APInt &N) {
- return APInt(N.getBitWidth(), N.countLeadingZeros());
- });
+ TestUnaryOpExhaustive(
+ [](const ConstantRange &CR) { return CR.ctlz(); },
+ [](const APInt &N) { return APInt(N.getBitWidth(), N.countl_zero()); });
TestUnaryOpExhaustive(
[](const ConstantRange &CR) { return CR.ctlz(/*ZeroIsPoison=*/true); },
[](const APInt &N) -> std::optional<APInt> {
if (N.isZero())
return std::nullopt;
- return APInt(N.getBitWidth(), N.countLeadingZeros());
+ return APInt(N.getBitWidth(), N.countl_zero());
});
}
diff --git a/llvm/unittests/IR/MetadataTest.cpp b/llvm/unittests/IR/MetadataTest.cpp
index 3b60a719780c7..85d394a9fbb85 100644
--- a/llvm/unittests/IR/MetadataTest.cpp
+++ b/llvm/unittests/IR/MetadataTest.cpp
@@ -1610,7 +1610,7 @@ TEST_F(DIEnumeratorTest, get) {
TEST_F(DIEnumeratorTest, getWithLargeValues) {
auto *N = DIEnumerator::get(Context, APInt::getMaxValue(128), false, "val");
- EXPECT_EQ(128U, N->getValue().countPopulation());
+ EXPECT_EQ(128U, N->getValue().popcount());
EXPECT_EQ(N,
DIEnumerator::get(Context, APInt::getMaxValue(128), false, "val"));
EXPECT_NE(N,
diff --git a/llvm/unittests/Support/DivisionByConstantTest.cpp b/llvm/unittests/Support/DivisionByConstantTest.cpp
index 5d19bad748e49..c0b708e277f20 100644
--- a/llvm/unittests/Support/DivisionByConstantTest.cpp
+++ b/llvm/unittests/Support/DivisionByConstantTest.cpp
@@ -106,9 +106,9 @@ APInt UnsignedDivideUsingMagic(const APInt &Numerator, const APInt &Divisor,
unsigned Bits = Numerator.getBitWidth();
if (LZOptimization) {
- unsigned LeadingZeros = Numerator.countLeadingZeros();
+ unsigned LeadingZeros = Numerator.countl_zero();
// Clip to the number of leading zeros in the divisor.
- LeadingZeros = std::min(LeadingZeros, Divisor.countLeadingZeros());
+ LeadingZeros = std::min(LeadingZeros, Divisor.countl_zero());
if (LeadingZeros > 0) {
Magics = UnsignedDivisionByConstantInfo::get(
Divisor, LeadingZeros, AllowEvenDivisorOptimization);
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 117abc9b4f389..8c0dac30df4d3 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -374,7 +374,7 @@ processSTIPredicate(STIPredicateFunction &Fn,
unsigned RhsCountPopulation = Rhs.popcount();
return ((LhsCountPopulation < RhsCountPopulation) ||
((LhsCountPopulation == RhsCountPopulation) &&
- (Lhs.countLeadingZeros() > Rhs.countLeadingZeros())));
+ (Lhs.countl_zero() > Rhs.countl_zero())));
};
if (LhsMasks.first != RhsMasks.first)
diff --git a/mlir/lib/AsmParser/AttributeParser.cpp b/mlir/lib/AsmParser/AttributeParser.cpp
index 16e86e687d552..1a491bacae7e8 100644
--- a/mlir/lib/AsmParser/AttributeParser.cpp
+++ b/mlir/lib/AsmParser/AttributeParser.cpp
@@ -373,7 +373,7 @@ static std::optional<APInt> buildAttributeAPInt(Type type, bool isNegative,
} else if (width < result.getBitWidth()) {
// The parser can return an unnecessarily wide result with leading zeros.
// This isn't a problem, but truncating off bits is bad.
- if (result.countLeadingZeros() < result.getBitWidth() - width)
+ if (result.countl_zero() < result.getBitWidth() - width)
return std::nullopt;
result = result.trunc(width);
diff --git a/mlir/lib/Dialect/Math/IR/MathOps.cpp b/mlir/lib/Dialect/Math/IR/MathOps.cpp
index 194ba9f234534..5c93f9f7017c9 100644
--- a/mlir/lib/Dialect/Math/IR/MathOps.cpp
+++ b/mlir/lib/Dialect/Math/IR/MathOps.cpp
@@ -149,9 +149,8 @@ OpFoldResult math::SinOp::fold(FoldAdaptor adaptor) {
OpFoldResult math::CountLeadingZerosOp::fold(FoldAdaptor adaptor) {
return constFoldUnaryOp<IntegerAttr>(
- adaptor.getOperands(), [](const APInt &a) {
- return APInt(a.getBitWidth(), a.countLeadingZeros());
- });
+ adaptor.getOperands(),
+ [](const APInt &a) { return APInt(a.getBitWidth(), a.countl_zero()); });
}
//===----------------------------------------------------------------------===//
@@ -160,9 +159,8 @@ OpFoldResult math::CountLeadingZerosOp::fold(FoldAdaptor adaptor) {
OpFoldResult math::CountTrailingZerosOp::fold(FoldAdaptor adaptor) {
return constFoldUnaryOp<IntegerAttr>(
- adaptor.getOperands(), [](const APInt &a) {
- return APInt(a.getBitWidth(), a.countTrailingZeros());
- });
+ adaptor.getOperands(),
+ [](const APInt &a) { return APInt(a.getBitWidth(), a.countr_zero()); });
}
//===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp b/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
index c81f004ecf5f9..2b2d937d55d80 100644
--- a/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
+++ b/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
@@ -498,7 +498,7 @@ static std::tuple<APInt, APInt>
widenBitwiseBounds(const ConstantIntRanges &bound) {
APInt leftVal = bound.umin(), rightVal = bound.umax();
unsigned bitwidth = leftVal.getBitWidth();
- unsigned
diff eringBits = bitwidth - (leftVal ^ rightVal).countLeadingZeros();
+ unsigned
diff eringBits = bitwidth - (leftVal ^ rightVal).countl_zero();
leftVal.clearLowBits(
diff eringBits);
rightVal.setLowBits(
diff eringBits);
return std::make_tuple(std::move(leftVal), std::move(rightVal));
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