[Mlir-commits] [mlir] b4a1eab - [mlir][sparse] fixed typo in sparse tensor type attribute alias

[Aart Bik]

Author: Aart Bik
Date: 2021-08-04T08:57:52-07:00
New Revision: b4a1eab941bda4c56dca685749b59a99076caebe

URL: https://github.com/llvm/llvm-project/commit/b4a1eab941bda4c56dca685749b59a99076caebe
DIFF: https://github.com/llvm/llvm-project/commit/b4a1eab941bda4c56dca685749b59a99076caebe.diff

LOG: [mlir][sparse] fixed typo in sparse tensor type attribute alias

Reviewed By: grosul1, rriddle

Differential Revision: https://reviews.llvm.org/D107472

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
index 5668bdc2ef3e..e91c80616bf6 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
@@ -33,7 +33,6 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding",
     Example:
 
     ```mlir
-
     #DCSC = #sparse_tensor.encoding<{
       dimLevelType = [ "compressed", "compressed" ],
       dimOrdering = affine_map<(i,j) -> (j,i)>,
@@ -42,8 +41,7 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding",
     }>
 
 
-    ... tensor<8x8xf64, #DCSR> ...
-
+    ... tensor<8x8xf64, #DCSC> ...
     ```
   }];