[llvm-testresults] Cron <andrewl at fenris> sh /home/andrewl/llvm-alpha.sh

[Cron Daemon]

DEJAGNU TEST RESULTS:
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CFrontend/2003-08-18-SigSetJmp.c: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CodeGen/Generic/fp_to_int.ll: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CodeGen/Generic/llvm-ct-intrinsics.ll: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CodeGen/Generic/vector.ll: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CodeGen/PowerPC/cttz.ll: 

DEJAGNU STATISTICS:
  # of expected passes		1291
  # of unexpected failures	5
  # of expected failures		37
cvs history: CVS password file /home/andrewl/.cvspass does not exist - creating a new file

USERS WHO COMMITTED:
  evancheng
  jlaskey
  lattner
  reid

ADDED FILES:
  llvm/test/Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
  llvm/test/Regression/CodeGen/PowerPC/vec_zero.ll
  llvm/test/Regression/CodeGen/X86/vec_zero.ll

CHANGED FILES:
  llvm-test/MultiSource/Applications/Burg/.cvsignore
  llvm-test/MultiSource/Applications/JM/ldecod/.cvsignore
  llvm-test/MultiSource/Applications/JM/ldecod/data/.cvsignore
  llvm-test/MultiSource/Applications/JM/lencod/.cvsignore
  llvm/Makefile.rules
  llvm/docs/HowToReleaseLLVM.html
  llvm/docs/LangRef.html
  llvm/docs/SourceLevelDebugging.html
  llvm/include/llvm/IntrinsicInst.h
  llvm/include/llvm/Intrinsics.td
  llvm/include/llvm/Target/MRegisterInfo.h
  llvm/include/llvm/Target/SubtargetFeature.h
  llvm/lib/CodeGen/DwarfWriter.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/Target/Alpha/AlphaRegisterInfo.td
  llvm/lib/Target/IA64/IA64RegisterInfo.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/lib/Target/PowerPC/README.txt
  llvm/lib/Target/README.txt
  llvm/lib/Target/Sparc/SparcRegisterInfo.td
  llvm/lib/Target/SubtargetFeature.cpp
  llvm/lib/Target/Target.td
  llvm/lib/Target/TargetSelectionDAG.td
  llvm/lib/Target/X86/README.txt
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrFPStack.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrMMX.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
  llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
  llvm/lib/VMCore/IntrinsicInst.cpp
  llvm/test/Regression/CodeGen/X86/overlap-add.ll
  llvm/test/Regression/CodeGen/X86/overlap-shift.ll
  llvm/utils/TableGen/CodeGenIntrinsics.h
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/DAGISelEmitter.cpp
  llvm/utils/TableGen/DAGISelEmitter.h
  llvm/utils/TableGen/IntrinsicEmitter.cpp
  llvm/utils/TableGen/RegisterInfoEmitter.cpp