[llvm-dev] scratch register for spill/reload

[David Callahan via llvm-dev]

I have a target architecture with a register class that requires a GPR as a scratch register to implement spill and reload operations. I have experimented with just using a pseudo instruction then scavenging a GPR on demand when that pseudo is lowered but that is not robust. Is there a protocol to allow a point GPR to be allocated when a spill or reload is generated?
I tried to add a suitable virtual register as an implicit def, but this failed, at least in the fast register allocator, because the generated instruction is apparently not visited.
My fall back was to add an implicit definition of an ABI defined scratch physical register. That generated incorrect code for some tests with the default allocator.
How have other targets managed this problem?
Thanks
david


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