[llvm-dev] Tablegen backend for emulator core?

[John Byrd via llvm-dev]

Howdy llvm-dev,

Low priority question.  This doesn't really meet the requirements for an
RFC, because it's probably merely a half-baked idea at this point.

As I was working with some tablegen internals on an 8-bit processor
backend, it struck me that I would need at some point to write an emulator
for that processor.

And I realized that, although I could write an emulator in the traditional
manner, tablegen already has most of the information it needs to
automatically generate the guts of an emulator.

Tablegen's already generating a disassembler (-gen-disassembler).

At the least, tablegen could be given an additional backend that says,
"given this instruction, do this emulation step."  Such a step could be
pure code copied from the .td files, or it could be compositionally
constructed based on the classes that an object is composed from.

You'd have to write your own code to deal with emulated machine state, but
hey, instruction parsing would be an item off the to-do list.

I would have a hard time believing that this concept is novel.  Has anyone
else taken a crack at this?

Sincerely,

-- 
---

John Byrd
Gigantic Software
2321 E 4th Street
Suite C #429
Santa Ana, CA  92705-3862
http://www.giganticsoftware.com
T: (949) 892-3526 F: (206) 309-0850
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