[llvm-dev] "Bits value must be constants" when generating ISel from Tablegen

[Paul C. Anagnostopoulos via llvm-dev]

Sorry, which TableGen backend is processing this?

I will need definitions for GP8 and REB is order to process your example. 


At 1/1/2021 10:45 PM, Zhang wrote:
>Hi Paul:
>Thanks for the help. I've reduced my test case to the snippet below:
>```
>class InstTest<bits<8> opcode,string asm,dag outs,dag ins,bits<2> regType> : Instruction{
>    bits<8> imm;
>    bits<8> dst;
>    field bits<32> Inst;
>    let Inst{7-0} = imm;
>    let Inst{8-15} = dst;
>    let OutOperandList = outs;
>    let InOperandList = ins;
>    let AsmString = asm;
>}
>class InstTest2<bits<8> opcode,string asm,dag outs,dag ins,bits<2> regType> : Instruction{
>    field bits<32> Inst;
>    let Inst{7-0} = 0b00000000;
>    let Inst{8-15} = 0b00000000;
>    let OutOperandList = outs;
>    let InOperandList = ins;
>    let AsmString = asm;
>}
>def RI : InstTest2<0x1,"test $dst,$imm",(outs GP8:$dst),(ins i8imm:$imm),REB>{
>    let Pattern = [(set GP8:$dst,(i8 imm:$imm))];
>}
>```
>
>Test2 works but InstTest doesn't. It seems the mere presence of the two bits<8> field causes this issue