[llvm-dev] "Bits value must be constants" when generating ISel from Tablegen

[Zhang via llvm-dev]

Hi Paul:
Thanks for the help. I've reduced my test case to the snippet below:
```
class InstTest<bits<8> opcode,string asm,dag outs,dag ins,bits<2> regType> : Instruction{
    bits<8> imm;
    bits<8> dst;
    field bits<32> Inst;
    let Inst{7-0} = imm;
    let Inst{8-15} = dst;
    let OutOperandList = outs;
    let InOperandList = ins;
    let AsmString = asm;
}
class InstTest2<bits<8> opcode,string asm,dag outs,dag ins,bits<2> regType> : Instruction{
    field bits<32> Inst;
    let Inst{7-0} = 0b00000000;
    let Inst{8-15} = 0b00000000;
    let OutOperandList = outs;
    let InOperandList = ins;
    let AsmString = asm;
}
def RI : InstTest2<0x1,"test $dst,$imm",(outs GP8:$dst),(ins i8imm:$imm),REB>{
    let Pattern = [(set GP8:$dst,(i8 imm:$imm))];
}

```


Test2 works but InstTest doesn't. It seems the mere presence of the two bits<8> field causes this issue
 
 
------------------ Original ------------------
From:  "llvm-dev"<llvm-dev at lists.llvm.org>;
Date:  Fri, Jan 1, 2021 00:12 AM
To:  "llvm-dev"<llvm-dev at lists.llvm.org>; 

Subject:  Re: [llvm-dev] "Bits value must be constants" when generating ISel from Tablegen

 

Please post the full definitions of InstRI8 and InstRI8222, along with the full definition of X and the record that inherits from InstRI8222. Then I can reproduce the problem and try to help you.

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