[llvm-dev] Query: Association of SchecWriteRes to instruction via InstRW records

[Dasgupta, Sandeep via llvm-dev]

Hello Team,
I have the following question relate to how to associate multiple SchedWriteRes with the same schedule model to a particular instruction.

For AArch64 target, at line<https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L262> <https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L262> , we have

def KryoWrite_3cyc_XY_noRSV_163ln :
SchedWriteRes<[KryoUnitXY]> {
let Latency = 3; let NumMicroOps = 2;}

def : InstRW<[KryoWrite_3cyc_XY_noRSV_163ln],
(instregex "(S|U)QXTU?N(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)")>;

Similarly, at line<https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L2366><https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L2366>,

def KryoWrite_1cyc_XY_noRSV_215ln :
SchedWriteRes<[KryoUnitXY]> {
let Latency = 1; let NumMicroOps = 2;
}
def : InstRW<[KryoWrite_1cyc_XY_noRSV_215ln],
(instregex "XTNv.*")>;

Both the InstRW records can match instruction SQXTNv16i8 and both have SchedModel == KryoModel (because of this<https://github.com/llvm/llvm-project/blob/2c062f2e89a9d48dde61dff835602bc3c5b5b0be/llvm/lib/Target/AArch64/AArch64SchedKryo.td#L59>).
However, the corresponding SchedWriteRes'es have different latencies. I am not sure which one of the two SchedWriteRes are going to be applied for the matched instruction.


Another similar situation: There are other cases like in lines here<https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L1853> and here<https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L1849>

def KryoWrite_1cyc_LS_Y_XY_305ln :
SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY]> {
let Latency = 1; let NumMicroOps = 3;
}
def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_305ln],
(instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;


def KryoWrite_1cyc_LS_Y_X_301ln :
SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> {
let Latency = 1; let NumMicroOps = 3;
}
def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_301ln],
(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))_POST$")>;

Both match ST1Twov2s_POST both have SchedModel == KryoModel, but the corresponding SchedSriteRes have different proc resources. Again, not sure which one to consider for the matched instruction.



Thanks,
Sandeep Dasgupta

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