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Hello Team,</div>
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I have the following question relate to how to associate multiple SchedWriteRes with the same schedule model to a particular instruction. </div>
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For AArch64 target, at <a href="https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L262" title="https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L262">
line</a> <a href="https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L262" target="_blank" data-saferedirecturl="https://www.google.com/url?q=https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td%23L262&source=gmail&ust=1629999018423000&usg=AFQjCNGHZHLTGk4b6A9KxiDB9w0RGpUr_w"></a>,
we have
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<font face="times new roman, serif"><span style="font-family: Consolas, Courier, monospace;">def KryoWrite_3cyc_XY_noRSV_163ln :</span><br>
<span style="font-family: Consolas, Courier, monospace;">SchedWriteRes<[KryoUnitXY]> {
</span><br>
<span style="font-family: Consolas, Courier, monospace;">let <b>Latency = 3</b>; let NumMicroOps = 2;}</span><br>
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<span style="font-family: Consolas, Courier, monospace;">def : InstRW<[KryoWrite_3cyc_XY_</span><wbr><span style="font-family: Consolas, Courier, monospace;">noRSV_163ln],
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<span style="font-family: Consolas, Courier, monospace;">(instregex "(S|U)QXTU?N(v16i8|v8i16|</span><wbr><span style="font-family: Consolas, Courier, monospace;">v4i32|v8i8|v4i16|v2i32)")>;</span></font><br>
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<div>Similarly, at <a href="https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L2366" title="https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L2366">
line</a><a href="https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L2366" target="_blank" data-saferedirecturl="https://www.google.com/url?q=https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td%23L2366&source=gmail&ust=1629999018423000&usg=AFQjCNEOMvacbUqYb4KPA8p3yGb9CFfUzg"></a>,</div>
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<div><span style="font-family: Consolas, Courier, monospace;">def KryoWrite_1cyc_XY_noRSV_215ln :</span><br>
<span style="font-family: Consolas, Courier, monospace;">SchedWriteRes<[KryoUnitXY]> {</span><br>
<span style="font-family: Consolas, Courier, monospace;">let <b>Latency = 1</b>; let NumMicroOps = 2;</span><br>
<span style="font-family: Consolas, Courier, monospace;">}</span><br>
<span style="font-family: Consolas, Courier, monospace;">def : InstRW<[KryoWrite_1cyc_XY_</span><wbr><span style="font-family: Consolas, Courier, monospace;">noRSV_215ln],</span><br>
<span style="font-family: Consolas, Courier, monospace;">(instregex "XTNv.*")>;</span><br>
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<div>Both the InstRW records can match instruction SQXTNv16i8 and both have SchedModel == KryoModel (because of
<a href="https://github.com/llvm/llvm-project/blob/2c062f2e89a9d48dde61dff835602bc3c5b5b0be/llvm/lib/Target/AArch64/AArch64SchedKryo.td#L59" title="https://github.com/llvm/llvm-project/blob/2c062f2e89a9d48dde61dff835602bc3c5b5b0be/llvm/lib/Target/AArch64/AArch64SchedKryo.td#L59">
this</a>). </div>
<div>However, the corresponding SchedWriteRes'es have different latencies. I am not sure which one of the two SchedWriteRes are going to be applied for the matched instruction.</div>
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<div>Another similar situation: There are other cases like in lines <a href="https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L1853" target="_blank" data-saferedirecturl="https://www.google.com/url?q=https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td%23L1853&source=gmail&ust=1629999018423000&usg=AFQjCNHyr7Qb-T3efdTTCRgeaarWuanZMw">here</a> and
<a href="https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td#L1849" target="_blank" data-saferedirecturl="https://www.google.com/url?q=https://github.com/llvm/llvm-project/blob/11b7ee974a69cabb379b12ce62a808594a53ef95/llvm/lib/Target/AArch64/AArch64SchedKryoDetails.td%23L1849&source=gmail&ust=1629999018423000&usg=AFQjCNF7c0uJDGS3dNy02nMVWFyeEznjuQ">
here</a></div>
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<div><font face="times new roman, serif"><span style="font-family: Consolas, Courier, monospace;">def KryoWrite_1cyc_LS_Y_XY_305ln :</span><br>
<span style="font-family: Consolas, Courier, monospace;">SchedWriteRes<[<b>KryoUnitLS, KryoUnitY, KryoUnitXY</b>]> {</span><br>
<span style="font-family: Consolas, Courier, monospace;">let Latency = 1; let NumMicroOps = 3;</span><br>
<span style="font-family: Consolas, Courier, monospace;">}</span><br>
<span style="font-family: Consolas, Courier, monospace;">def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_305ln],</span><br>
<span style="font-family: Consolas, Courier, monospace;">(instregex "ST1(One(v16b|v8h|v4s|v2d)|</span><wbr><span style="font-family: Consolas, Courier, monospace;">Two(v8b|v4h|v2s|v1d))_POST$")></span><wbr><span style="font-family: Consolas, Courier, monospace;">;</span></font><br>
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<div><font face="times new roman, serif"><span style="font-family: Consolas, Courier, monospace;">def KryoWrite_1cyc_LS_Y_X_301ln :</span><br>
<span style="font-family: Consolas, Courier, monospace;">SchedWriteRes<[<b>KryoUnitLS, KryoUnitY, KryoUnitX</b>]> {</span><br>
<span style="font-family: Consolas, Courier, monospace;">let Latency = 1; let NumMicroOps = 3;</span><br>
<span style="font-family: Consolas, Courier, monospace;">}</span><br>
<span style="font-family: Consolas, Courier, monospace;">def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_301ln],</span><br>
<span style="font-family: Consolas, Courier, monospace;">(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|</span><wbr><span style="font-family: Consolas, Courier, monospace;">v8h|v4s|v2d)|(i8|i16|i32|i64)|</span><wbr><span style="font-family: Consolas, Courier, monospace;">Two(v8b|v4h|v2s|v1d))_POST$")></span><wbr><span style="font-family: Consolas, Courier, monospace;">;</span><br>
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Both match ST1Twov2s_POST <span style="background-color:rgb(255, 255, 255);display:inline !important">
both have SchedModel == KryoModel</span>, but the corresponding SchedSriteRes have different proc resources. Again, not sure which one to consider for the matched instruction. <br>
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Thanks,</div>
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Sandeep Dasgupta</div>
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