[llvm-dev] How to get started with VLIW scheduler?

Krzysztof Parzyszek via llvm-dev llvm-dev at lists.llvm.org
Mon Apr 26 13:01:43 PDT 2021

The way we do it for Hexagon is that we have our own specialization of the MachineScheduler pass, followed by a packetizer pass.  Actually, we run two schedulers: machine scheduler, and post-RA scheduler, but that doesn’t change much conceptually.  In the scheduler passes we don’t form instruction packets, at least not explicitly.  We do some sort of a simulation of “what if we were forming packets right now” type of thing, maximizing packetization opportunities ahead of time, before the packetization itself, hoping that enough of it will prevail.

Finally, near the end of the post-RA passes we do run the DFAPacketizer pass which forms the actual packets (i.e. “bundles” in LLVM terminology).  The DFA packetizer relies on tables that are generated out of your target’s td files describing your processor’s resources (some of which the standard scheduler uses as well).

If you’re starting from scratch, I’d get the packetizer working first.

Krzysztof Parzyszek  kparzysz at quicinc.com<mailto:kparzysz at quicinc.com>   AI tools development

From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of jeniffer lesley via llvm-dev
Sent: Monday, April 26, 2021 1:33 PM
To: llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] [llvm-dev] How to get started with VLIW scheduler?

I am building a toy target to teach at a university but I am not well aware of LLVM's scheduler infrastructure. My target is VLIW, 1 Load, 1 Store and 2 ALUs. ALUs can perform almost all common mathematical operations.

Where do I start building a scheduler for it? I watched a couple of videos from the LLVM dev meeting but what is the current way of building a new scheduler? Is there a .rst page out there which I missed reading?

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