[llvm-dev] Simulation of load-store forwarding with MI scheduler on AArch64

[Evgeny Leviant via llvm-dev]

Hi list,

Is it possible to simulate load to store forwarding on aarch64 with MI scheduling model on AArch64?
For instance $x0 data latency in the example below should be 1 cycle

ldr $x0, [$x1]
str $x0, [$x2]

But it should be 4 cycles if we have another instruction:

ldr $x0, [$x1]
add $x0, $x0, 4

For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how
to do this with WriteLD or WriteST. Is there some workaround?
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