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<p class="MsoNormal"><span lang="EN-US">Hi list,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Is it possible to simulate load to store forwarding on aarch64 with MI scheduling model on AArch64?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">For instance $x0 data latency in the example below should be 1 cycle<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">ldr $x0, [$x1]<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">str $x0, [$x2]<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">But it should be 4 cycles if we have another instruction:<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">ldr $x0, [$x1]<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">add $x0, $x0, 4<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">to do this with WriteLD or WriteST. Is there some workaround?</span><o:p></o:p></p>
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