[llvm-dev] The order of the registers in XXXGenRegisterInfo.inc

[Simon de Vegt via llvm-dev]

Hi all,

Can anyone explain how the order of the registers in XXXGenRegisterInfo.inc is determined?

E.g. for RISCV:
namespace RISCV {
enum {
  NoRegister,
 X0 = 1,
  X1 = 2,
  // (...)
  F31_F = 96,
  NUM_TARGET_REGS // 97
};
}

How does this relate to the content of the XXXRegisterInfo.td file? It seems like the enum is generated with the same ordering as the register records appear when running llvm-tblgen.
I have shuffled with my definitions but don't seem to be able to influence this order.

Root issue:
My architecture has specific registers for constants, a separate register class. I run a pre-regalloc allocator to allocate constants to registers from that class (because they need to be persistent and not be reused etc).
I can simply 'MO.setReg(constRegId++)' in my allocator but then I would need to know the number of the register, which apparently is not the same as the one defined in my XXXRegisterInfo.td file:
foreach regid = 447-510 in {
  def C#regid : XXXConstReg<regid, "c"#regid, ["c"#regid]>, DwarfRegNum<[regid]>;
}

If there is a way to get the register range for a certain register class such that I can allocate machine operands to a physical register in that class, then that would solve my issue.

Mvg Simon de Vegt
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20201126/1613427c/attachment-0001.html>