[llvm-dev] Different regs on the same list!

[Bagel via llvm-dev]

What I am trying to do is replace three instructions:
   %34:gregs = nuw ADDri %34:gregs, 1
   %26:gregs = CMPrr %32:gregs, %34:gregs
   BRIB %bb.5, %26:gregs, 10
with one LOOP instruction that does the work of all three
   LOOP 10,%34:gregs,%32:gregs,1
// %bb.5 is implicit because the top of the loop has been marked with another 
//instruction
After I build the loop instruction I use eraseFromParent() to remove the ADDri, 
CMPrr, BRIB instructions.
The assertion trips when I add the %34:gregs operand. Should I be removing the 
replace instruction *before* I build the replacement?

Thanks,
brian


On 12/15/20 1:36 PM, Craig Topper wrote:
> All MachineOperand's that use or define a particular virtual/physical register 
> are kept in a linked list. There is a separate list for each register. This 
> assert is checking that the register being added is consistent with other nodes 
> in the list it is being added to. There's a map that is referenced 
> by getRegUseDefListHead to find the linked list for a particular register. So 
> it seems like in your case the list and/or map have gotten out of sync somehow. 
> I'm not sure what you're doing wrong to get into this state. Most APIs know 
> about the lists and keep them updated. For example, MachineOperand::setReg 
> removes the old register from its list before changing it.
> 
> On Tue, Dec 15, 2020 at 10:59 AM Bagel via llvm-dev <llvm-dev at lists.llvm.org 
> <mailto:llvm-dev at lists.llvm.org>> wrote:
> 
>     What causes this assertion in lib/Codegen/MachineRegisterInfo.cpp?  I am
>     building a MachineInstruction with a register operand and get this for certain
>     registers.  What is the "list" keeping track of?  Any idea what I'm doing
>     wrong?
> 
>     Thanks,
>     brian
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