[llvm-dev] How to represent two-address instruction with TableGen?

[Diogo Sampaio via llvm-dev]

Hi Zhang, 
I am not sure this is the only, nor the best, way to do it, but in our backend we define a "fake" input operand for two operands instructions. And we add the constraint of the first input being the same register of the output: 

let Constraints = "$in0 = $out" in 
def MY_INSTRUCTION : MY_INSTRUCTION_CLASS 
<(outs MyRegClass:$out), (ins MyRegClass:$in0, MyRegClass:$in1) 

I guess such constraints could be all the way in your instruction classes definitions. 
Hope that was clear enough. 

Cheers 
Diogo 


From: "llvm-dev" <llvm-dev at lists.llvm.org> 
To: "llvm-dev" <llvm-dev at lists.llvm.org> 
Sent: Monday, December 14, 2020 9:23:16 AM 
Subject: [llvm-dev] How to represent two-address instruction with TableGen? 

Hi: 
I'm new to LLVM backend and is developing for a custom ISA which instruction has two addresses. 
For example: 
add $r0,$1 means r0=r0+r1. 

Previously I just declare two operands for add as following: 

``` 
"add $dst,$src" 
(outs GPR64:$dst) 
(ins GPR64:$src) 
``` 

However when I tried to add ISel patterns to this instruction with the following pattern: 

``` 
(set GPR64:$dst,(add GPR64:$src,GPR64:$dst)) 
``` 

I received error: 

``` 
In ADDRR: Input operand $dst occurs in pattern but not in operands list! 
``` 

Not sure about what I did wrong here, any hint would be much appreciate 


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