<html><body><div style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #000000">Hi Zhang,<br>I am not sure this is the only, nor the best, way to do it, but in our backend we define a "fake" input operand for two operands instructions. And we add the constraint of the first input being the same register of the output:<br><br>let Constraints = "$in0 = $out" in<br>def MY_INSTRUCTION : MY_INSTRUCTION_CLASS<br> <(outs MyRegClass:$out), (ins MyRegClass:$in0, MyRegClass:$in1)<br><br>I guess such constraints could be all the way in your instruction classes definitions.<br>Hope that was clear enough.<br><br>Cheers<br>Diogo<br><br><hr id="zwchr" data-marker=""><div data-marker=""><b>From: </b>"llvm-dev" <llvm-dev@lists.llvm.org><br><b>To: </b>"llvm-dev" <llvm-dev@lists.llvm.org><br><b>Sent: </b>Monday, December 14, 2020 9:23:16 AM<br><b>Subject: </b>[llvm-dev] How to represent two-address instruction with TableGen?<br></div><br><div data-marker=""><div>Hi:</div><div>I'm new to LLVM backend and is developing for a custom ISA which instruction has two addresses.</div><div>For example:</div><div>add $r0,$1 means r0=r0+r1.</div><br><div>Previously I just declare two operands for add as following:</div><br><div>```</div><div>"add $dst,$src"</div><div>(outs GPR64:$dst)</div><div>(ins GPR64:$src)</div><div>```</div><br><div>However when I tried to add ISel patterns to this instruction with the following pattern:</div><br><div>```</div><div>(set GPR64:$dst,(add GPR64:$src,GPR64:$dst))</div><div>```</div><br><div>I received error:</div><br><div>```</div><div>In ADDRR: Input operand $dst occurs in pattern but not in operands list!</div><div>```</div><br><div>Not sure about what I did wrong here, any hint would be much appreciate</div><br><br>_______________________________________________<br>LLVM Developers mailing list<br>llvm-dev@lists.llvm.org<br>https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev<br></div></div></body></html>