[llvm-dev] New NEC SX-Aurora target

[Simon Moll via llvm-dev]

Hi,

We are looking for reviewers for https://reviews.llvm.org/D69103 , which registers a target stub for the NEC SX-Aurora Vector Engine.

(Summary)

This patch registers the 've' target: the NEC SX-Aurora TSUBASA Vector Engine.

This follows up on the announcement on llvm-dev: https://lists.llvm.org/pipermail/llvm-dev/2019-April/131580.html
We have a poster & lightning talk at the upcoming DevMtg: http://llvm.org/devmtg/2019-10/talk-abstracts.html#lit6

  *   Public documentation (architecture, encodings, instructions)
     *   ISA manual: https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf
     *   Up-to-date documentation on architecture and tools: https://www.hpc.nec/documents/

  *   Reference implementation
     *   github: https://github.com/sx-aurora-dev/llvm-project
     *   Status: full scalar instruction support, clang toolchain integration, vector support through intrinsics.

  *   Testing
     *   Reference implementation is tested continuously at NEC.
     *   We are planning to setup a buildslave reporting to LLVM buildmaster.

  *   Code owner of the VE target
     *   Simon Moll

A rough roadmap:

  1.  Registers, encodings, scalar instructions, clang tooling, ..
  2.  Vector instruction support through target-specific intrinsics.
  3.  Support for LLVM-VP<https://reviews.llvm.org/D57504> as it becomes available in LLVM upstream.


Thanks

- Simon
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