[llvm-dev] Which way to lower selects on architectures without conditional moves&
Craig Topper via llvm-dev
llvm-dev at lists.llvm.org
Fri Oct 11 16:34:47 PDT 2019
SelectionDAG can't have control flow. For X86 we match selects on old CPUs
or on types that don't support cmov to pseudo cmov instructions during
isel. Those cmov instructions are marked as "UsesCustomInserter" in the
InstrInfo td files. X86TargetLowering::EmitInstrWithCustomInserter will
then expand those pseudo instructions into control flow by creating new
MachineBasicBlocks and branches. Most of that code is
On Fri, Oct 11, 2019 at 4:20 PM s.ignatov via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> We have the architecture without conditional moves. Which way can we
> lower select?
> As we know there was the special pass a long time ago, but it was deleted.
> commit c3591a0d48ce045bbf5ae0d78a41f3dae4bb99db
> Author: Chris Lattner <sabre at nondot.org>
> Date: Tue Feb 19 07:49:17 2008 +0000
> remove the LowerSelect pass. The last client was the old Sparc
> backend, which is long dead by now.
> llvm-svn: 47323
> The problem is that if we use this pass we lose some useful special
> optimizing cases for selects, e.g. replacing it by min/max.
> Does anyone have some experience with such architecture?
> We're trying to generate some "if-then-else" on SelectionDAG now.
> Could anyone show the way to generate "if-then-else" constructs on
> Thanks in advance,
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
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