[llvm-dev] Data flow graph with latency
Alexey Zhikhartsev via llvm-dev
llvm-dev at lists.llvm.org
Fri Oct 11 08:34:56 PDT 2019
Instruction latency is target-dependent, so midend IR does not have it.
Latencies can be found in instruction scheduling DAGs, although be aware
that they are local (I.e., per basic block).
On Thu., Oct. 10, 2019, 12:27 a.m. 이수연 via llvm-dev, <
llvm-dev at lists.llvm.org> wrote:
> I'm looking for the method to print out the Data Flow Graph(DFG) which has
> edges labeled with latency.
> Is it possible to generate it from LLVM IR?
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
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