[llvm-dev] Instruction is selected, but it shouldn't (?)

[Eli Friedman via llvm-dev]

SelectionDAG isel is only driven by types and operations; it doesn't care about specific registers.  So you have to pick one version of "add" you want isel to use by default (in this case, probably the general-register version), and only specify a pattern for that one.

For computing the addresses of stack slots in particular, you might want to look at how the ARM backend generates Thumb1 code.  Thumb1 has special instructions for SP-relative accesses (tADDframe, tADDrSP, tADDrSPi, tLDRspi, tSTRspi). Explicit copies from "sp" don't really come up during isel, except for call arguments; most of the interesting code is part of frame lowering.

-Eli

From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Joan Lluch via llvm-dev
Sent: Tuesday, May 28, 2019 11:31 AM
To: via llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] [llvm-dev] Instruction is selected, but it shouldn't (?)

In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register:

def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>;
def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>;

The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTargetInstrInfo.td:

class T5rr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<4> opcode>: Type5
                <opcode,
                (outs GR16:$rd), (ins GR16:$rn, GR16:$rs),
                AsmStr< opcStr, altOpcStr, "\t$rn, $rs, $rd">.n,
                [(set GR16:$rd, (opNode GR16:$rn, GR16:$rs)), (implicit SR)]>;

I also have specific instructions that can only use the SP, so I defined this as well

class T11sr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<3> opcode, bits<2> mode>: Type11
                <opcode, mode,
                (outs GR16:$rd), (ins SSP:$sp, GR16:$rd0),
                AsmStr< opcStr, altOpcStr, "\t$sp, $rd0, $rd">.n,
                [(set GR16:$rd, (opNode SSP:$sp, GR16:$rd0)), (implicit SR)]>
                {let Constraints = "$rd = $rd0";}


According to my understanding, instructions belonging to the T5rr16alu class above, should never be selected with the SP as register. However, instructions of that class get selected anyway with the SP, instead of the class T11sr16alu.

However, if I place class T11sr16alu, before class T5rr16alu, then the right instruction is selected

Why is that?.
What I am missing?

Joan

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190528/8c9327d9/attachment-0001.html>