[llvm-dev] Instruction is selected, but it shouldn't (?)

Joan Lluch via llvm-dev llvm-dev at lists.llvm.org
Tue May 28 11:30:47 PDT 2019

In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register:

def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>;
def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>;

The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTargetInstrInfo.td:

class T5rr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<4> opcode>: Type5
                (outs GR16:$rd), (ins GR16:$rn, GR16:$rs),
                AsmStr< opcStr, altOpcStr, "\t$rn, $rs, $rd">.n,
                [(set GR16:$rd, (opNode GR16:$rn, GR16:$rs)), (implicit SR)]>;

I also have specific instructions that can only use the SP, so I defined this as well

class T11sr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<3> opcode, bits<2> mode>: Type11
                <opcode, mode,
                (outs GR16:$rd), (ins SSP:$sp, GR16:$rd0),
                AsmStr< opcStr, altOpcStr, "\t$sp, $rd0, $rd">.n,
                [(set GR16:$rd, (opNode SSP:$sp, GR16:$rd0)), (implicit SR)]>
                {let Constraints = "$rd = $rd0";}

According to my understanding, instructions belonging to the T5rr16alu class above, should never be selected with the SP as register. However, instructions of that class get selected anyway with the SP, instead of the class T11sr16alu.

However, if I place class T11sr16alu, before class T5rr16alu, then the right instruction is selected

Why is that?. 
What I am missing?


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