[llvm-dev] RegAlloc Q: spill when implicit-def physreg is also the output reg of instruction

[Kevin Choi via llvm-dev]

Hi LLVM,

I ran into a case where RegAlloc would insert a spill across instruction 
that had same register for output operand and implicit-def. The effect 
this had was that spill code would immediately overwrite the output 
result. Is this the expected result of setting up MyInst this way? In 
other words, does RegAlloc know to not insert spill in case it sees that 
output reg is same as one of implicit-def?

If this is intended (always spilling live regs across implicit-def 
inst?), I am puzzled on how to use MyInst that has variable output reg 
with static implicit-defs. Any tips would be greatly appreciated.

Reduced Example:

_*Before RegAlloc:*_
%1:reg = COPY ...;
%2:reg = MyInst %1:reg, ..., implicit-def dead $p1, ...;
%3:reg = Use %2:reg

_*RegAlloc:*_
 >> %2:reg = MyInst %1:reg, ..., implicit-def dead $p1, ...;
Regs: $p1=%1
Killing last use: %1:reg
Assigning %2 to $p1
Spilling %2 in $p1 to stack slot #2  <-- suspicious if this is inserting 
spill, unaware of output reg being same
<< $p1 =MyInst killed $p1, ..., implicit-def dead $p1, ...;

*_After RegAlloc:_*
$p1 = COPY ...;
Store $p1 %stack.2;
$p1 =MyInst killed $p1, ..., implicit-def dead $p1, ...;
$p1 = Load %stack.2;
$p2 = Use $p1, ...;


Best Regards,

Kevin

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