<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=UTF-8">
</head>
<body text="#000000" bgcolor="#FFFFFF">
<p>Hi LLVM,</p>
<p>I ran into a case where RegAlloc would insert a spill across
instruction that had same register for output operand and
implicit-def. The effect this had was that spill code would
immediately overwrite the output result. Is this the expected
result of setting up MyInst this way? In other words, does
RegAlloc know to not insert spill in case it sees that output reg
is same as one of implicit-def?</p>
<p>If this is intended (always spilling live regs across
implicit-def inst?), I am puzzled on how to use MyInst that has
variable output reg with static implicit-defs. Any tips would be
greatly appreciated.</p>
<p>Reduced Example:<br>
</p>
<p><u><b>Before RegAlloc:</b></u><br>
%1:reg = COPY ...;<br>
%2:reg = MyInst %1:reg, ..., implicit-def dead $p1, ...;<br>
%3:reg = Use %2:reg</p>
<u><b>RegAlloc:</b></u><br>
>> %2:reg = MyInst %1:reg, ..., implicit-def dead $p1, ...;<br>
Regs: $p1=%1<br>
Killing last use: %1:reg<br>
Assigning %2 to $p1<br>
Spilling %2 in $p1 to stack slot #2 <-- suspicious if this is
inserting spill, unaware of output reg being same<br>
<< $p1 =MyInst killed $p1, ..., implicit-def dead $p1, ...;
<p><b><u>After RegAlloc:</u></b><br>
$p1 = COPY ...;<br>
Store $p1 %stack.2;<br>
$p1 =MyInst killed $p1, ..., implicit-def dead $p1, ...;<br>
$p1 = Load %stack.2;<br>
$p2 = Use $p1, ...;</p>
<p><br>
</p>
<p>Best Regards,</p>
<p>Kevin<br>
</p>
</body>
</html>