[llvm-dev] Overlapping register groups in old 8-bit MC6809 processor.

[Mark R V Murray via llvm-dev]

> On 25 Mar 2019, at 15:15, Tim Northover <t.p.northover at gmail.com> wrote:
> 
> Hi Mark,
> 
> On Mon, 25 Mar 2019 at 14:49, Mark R V Murray via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
>> TableGen doesn't like that last line, the ALLREG group. I need it because the EXG and TFR instructions both take 2 register indices from either GR16 or GR8 (I'm happy to check that both are from the same group in C++ code if necessary, but right now I'm stuck with either specifying two operands from GR16 or 2 from GR8.
> 
> Have you considered modelling it as two separate instructions, TFR8
> and TFR16 for example? That seems like it'd fit into LLVM's ideas
> about register classes a lot more neatly, and as an added bonus it'd
> automatically enforce the size constraint.

I did think of that, in fact I tried it too, but as the instruction has the same opcode and mnemonic (the post-byte defines the registers used), and it's thus possible to encode (e.g.) "EXG A,D" (undefined result). I kept hitting "already defined" problems or the match table being degenerate.

Right now I'm getting disassembly pretty-much free-of-charge but without full use of EXG and TFR. I may try to code TFR.W vs TFR.B variants (again) but I was hoping not to get my hands that dirty in the disassembler.

> I don't have a solution though. I suspect ALLREG is fundamentally
> unsound as far as LLVM is concerned and this is just the tip of the
> iceberg.

Darn :-).

Thanks!

M
-- 
Mark R V Murray