[llvm-dev] Scalable Vector Types in IR - Next Steps?

[Erich Focht via llvm-dev]

On Mon, Mar 18, 2019 at 18:16:42 Jacob Lifshay via llvm-dev
<llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>
>     Three ISAs at present:
>
>     - SVE in Aarch64
>     - MVE in ARM Cortex-M (quite different from SVE)
>     - RVV in RISC-V
>
>     It would not surprise me if other ISAs implement similar vector
>     extensions in future.
>
> We're planning on implementing scalable vector support in the SimpleV
> ISA extension as well. Admittedly, we will most likely need additional
> IR modifications (allowing vectors of vectors), but I think having
> scalable vector support already built in will help greatly.
>
As Simon Moll also wrote, please add the NEC SX-Aurora vector engine to
the list of architectures aiming at and awaiting eagerly the SVE/AVL/VP
changes in LLVM. We have long vectors (256x64bit) and a vector length
register since many years, with the latest CPU being available on the
market since a year, mainly aiming at HPC and AI.

We're working on an LLVM backend and intend to open it and post an RFC
on its inclusion soon. Progress with AVL/VP is very important for this
backend and we rely on LLVM moving forward on these.

Regards,
Erich Focht